# US 11,444,186 B2 · Semiconductor device

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- Number: US 11,444,186 B2
- Document ID: US11444186B2
- Status: Granted
- Kind: B2
- Application number: 17/082,802
- Filed: 2020-10-28
- Published: 2021-05-20
- Granted: 2022-09-13
- Earliest claimed: 2019-11-18
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Nao Nagata
- Web page: https://patentgrep.com/patent/US11444186B2

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 64/232: {Emitter electrodes for IGBTs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate, first and second trench electrodes formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first and second trench electrodes, a floating separation layer of a second conductivity type formed between the first and second trench electrodes and contacted with the floating layer of the first conductivity type and a floating layer control gate disposed on the floating separation layer of the second conductivity type.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
first and second trench electrodes formed in the semiconductor substrate;
a floating layer of a first conductivity type formed around the first and second trench electrodes;
a floating separation layer of a second conductivity type formed between the first and second trench electrodes and contacted with the floating layer of the first conductivity type; and
a floating layer control gate disposed above the floating separation layer of the second conductivity type.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a gate electrode to which a gate potential is supplied; and
an emitter electrode to which an emitter electrode is supplied,
wherein the first and second trench electrodes are first and second gate potential trench electrodes to which the gate potential is supplied, and
wherein the floating separation layer of the second conductivity type is coupled to the emitter electrode via a contact.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the first gate potential trench electrode has a linear portion extending in a first direction in a plan view, and a bent portion extending in a second direction, and
wherein the second gate potential trench electrode is a line-symmetrical shape with the first gate potential trench electrode with respect to a line parallel to the second direction.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the floating separation layer of the second conductivity type is disposed between the bent portion of the first gate potential trench electrode and the bent portion of the second gate potential trench electrode.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the bent portion extending in the second direction has a shape being bent from the linear portion in the second direction and returning to the linear portion.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4,
wherein the bent portion extending in the second direction has a shape being bent in a second direction from a first point of the linear portion and returning to a second point of the linear portion, and
wherein a distance between the first and second points is longer than a distance between the bent portion of the first gate potential trench electrode and the bent portion of the second gate potential trench electrode.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, further comprising:
a diffusion layer of the first conductivity type disposed on the floating separation layer of the second conductivity type.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, further comprising:
a diffusion layer of the second conductivity type disposed on the diffusion layer of the first conductivity type.

### Claim 9 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a body layer of the first conductivity type coupled to the emitter electrode through the contact,
wherein the floating separation layer of the second conductivity type is formed so as to cover the body layer of the first conductivity type.

### Claim 10 (depends on 2)

The semiconductor device according to claim 2, wherein the floating layer control gate is coupled to the gate electrode.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a gate electrode to which a gate potential is supplied; and
an emitter electrode to which an emitter potential is supplied,
wherein the first and second trench electrodes are first and second emitter potential trench electrodes to which the emitter potential is supplied, and
wherein the floating separation layer of the second conductivity type is coupled to the emitter electrode via a contact.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11,
wherein the first emitter potential trench electrode has a linear portion extending in a first direction in a plan view, and a bent portion extending in a second direction, and
wherein the second emitter potential trench electrode is a line-symmetrical shape with the first emitter potential trench electrode with respect to a line parallel to the second direction.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the floating separation layer of the second conductivity type is disposed between the bent portion of the first emitter potential trench electrode and the bent portion of the second emitter potential trench electrode.

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein the bent portion extending in the second direction has a shape being bent from the linear portion in the second direction and returning to the linear portion.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein the bent portion extending in the second direction has a shape being further bent in the first direction and returning to the bent portion extending in the second direction.

### Claim 16 (depends on 12)

The semiconductor device according to claim 12, further comprising:
a gate potential trench electrode to which the gate potential is supplied,
wherein the gate potential trench electrode is disposed in a region sandwiched between the first and second emitter potential trench electrodes, and
wherein the floating separation layer of the second conductivity type is disposed between the bent portion of the first emitter potential trench electrode and the gate potential trench electrode, and between the bent portion of the second emitter potential trench electrode and the gate potential trench electrode.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16, wherein the gate potential trench electrode has a linear portion extending in the first direction, and a shape being bent in the second direction from the linear portion and returning to the linear portion.

### Claim 18 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an active cell region formed in the semiconductor substrate; and
a termination region formed so as to surround the active cell region,
wherein a plurality of regions each of where the first and second trench electrode, the floating separation layer of the second conductivity type and the floating layer control gate are formed is arranged in the active cell region, and
wherein an arrangement density of the regions in a central portion of the active cell region is lower than an arrangement density of the regions in a vicinity of the termination region.

### Claim 19 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device is an IE-type IGBT.