# US 11,444,185 B2 · III-V lateral bipolar junction transistor on local facetted buried oxide layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,185 B2 - Document ID: US11444185B2 - Status: Granted - Kind: B2 - Application number: 16/661,518 - Filed: 2019-10-23 - Published: 2020-02-20 - Granted: 2022-09-13 - Earliest claimed: 2017-11-21 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Pouya Hashemi; Mahmoud Khojasteh; Tak H. Ning; Alexander Reznicek - Web page: https://patentgrep.com/patent/US11444185B2 ## CPC - H10D 10/80: Heterojunction BJTs - H10D 10/021: {of heterojunction BJTs [HBT]} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions - H10D 62/405: {Orientations of crystalline planes} - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10P 50/648: {Anisotropic liquid etching} - H10D 10/60: Lateral BJTs - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation. ## Claims ### Claim 1 A method of forming a bipolar junction transistor comprising: forming a III-V semiconductor material for a base region atop a III-V semiconductor substrate; forming emitter and collector regions on opposing sides of the base region; and etching the III-V semiconductor substrate selectively to facets having a {110} crystalline orientation to provide a trench having an inverted apex geometry underlying at least the base region, wherein an apex of the inverted apex geometry is positioned directly under the base region. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the emitter and collector regions comprises: forming a sacrificial extrinsic base structure on a channel portion of the III-V semiconductor material for the base region; removing exposed portions of the III-V semiconductor material for the base region selectively to the III-V semiconductor substrate; and epitaxially growing a III-V semiconductor material having a wider band gap than the III-V semiconductor material for the base region to provide the emitter and collector regions on the opposing sides of the base region. ### Claim 3 (depends on 2) The method of claim 2, wherein the III-V semiconductor substrate comprises indium phosphide (InP). ### Claim 4 (depends on 3) The method of claim 3, wherein said etching the III-V semiconductor substrate comprises: forming an interlevel dielectric layer having an upper surface coplanar with an upper surface of the sacrificial extrinsic base structure; etching portions of the III-V semiconductor material for the base region not covered by the sacrificial extrinsic base structure to expose the III-V semiconductor substrate; removing the sacrificial extrinsic base structure; and etching the III-V semiconductor substrate selectively to the facets having the {110} crystalline orientation with a hydrochloric acid containing wet etchant to provide the trench having the inverted apex geometry. ### Claim 5 (depends on 4) The method of claim 4, further comprising filling the trench having the inverted apex geometry with a dielectric material. ### Claim 6 (depends on 5) The method of claim 5, wherein the dielectric material is selected from the group consisting of organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and combinations thereof. ### Claim 7 (depends on 6) The method of claim 6, further comprising forming a functional extrinsic base structure. ### Claim 8 (depends on 1) The method of claim 1, wherein the trench having the inverted apex geometry provides an air gap in the bipolar junction transistor. ### Claim 9 (depends on 1) The method of claim 1, wherein the bipolar junction transistor is a lateral bipolar junction transistor. ### Claim 10 A method of forming a bipolar junction transistor comprising: forming a III-V semiconductor material for a base region atop a III-V semiconductor substrate; forming emitter and collector regions on opposing sides of the base region; etching the III-V semiconductor substrate selectively to facets having a {110} crystalline orientation to provide a trench having an inverted apex geometry underlying at least the base region, wherein an apex of the inverted apex geometry is positioned directly under the base region; and filling the trench having the inverted apex geometry with a dielectric material. ### Claim 11 (depends on 10) The method of claim 10, wherein forming the emitter and collector regions comprises: forming a sacrificial extrinsic base structure on a channel portion of the III-V semiconductor material for the base region; removing exposed portions of the III-V semiconductor material for the base region selectively to the III-V semiconductor substrate; and epitaxially growing a III-V semiconductor material having a wider band gap than the III-V semiconductor material for the base region to provide the emitter and collector regions on the opposing sides of the base region. ### Claim 12 (depends on 11) The method of claim 11, wherein the III-V semiconductor substrate comprises indium phosphide (InP). ### Claim 13 (depends on 12) The method of claim 12, wherein said etching the III-V semiconductor substrate comprises: etching portions of the III-V semiconductor material for the base region not covered by the sacrificial extrinsic base structure to expose the III-V semiconductor substrate; removing the sacrificial extrinsic base structure; and etching the III-V semiconductor substrate selectively to the facets having the {110} crystalline orientation with a hydrochloric acid containing wet etchant to provide the trench having the inverted apex geometry. ### Claim 14 (depends on 13) The method of claim 13, further comprising forming an interlevel dielectric layer having an upper surface coplanar with an upper surface of the sacrificial extrinsic base structure prior to said etching portions of the III-V semiconductor material. ### Claim 15 (depends on 14) The method of claim 14, wherein the dielectric material is selected from the group consisting of organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and combinations thereof. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming a functional extrinsic base structure. ### Claim 17 (depends on 10) The method of claim 10, wherein the bipolar junction transistor is a lateral bipolar junction transistor. ### Claim 18 A method of forming a semiconductor device comprising: forming a semiconductor material for a base region atop a semiconductor substrate; forming emitter and collector regions on opposing sides of the base region; and etching the semiconductor substrate selectively to facets having a {110} crystalline orientation to provide a trench having an inverted apex geometry underlying at least the base region, wherein an apex of the inverted apex geometry is positioned directly under the base region. ### Claim 19 (depends on 18) The method of claim 18, further comprising filling the trench having the inverted apex geometry with a dielectric material. ### Claim 20 (depends on 18) The method of claim 18, wherein the trench having the inverted apex geometry provides an air gap in the semiconductor device.