# US 11,444,184 B1 · System for induced quantum dots for material characterization, qubits, and quantum computers

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- Number: US 11,444,184 B1
- Document ID: US11444184B1
- Status: Granted
- Kind: B1
- Application number: 16/552,764
- Filed: 2019-08-27
- Granted: 2022-09-13
- Earliest claimed: 2018-08-27
- Assignees: U.S. Government as represented by the Director, National Security Agency
- Applicants: The Government of the Untied States as represented by the Director, National Security Agency
- Inventors: Charles George Tahan; Rousko Todorov Hristov; Yun-Pil Shim; Hilary Hurst
- Web page: https://patentgrep.com/patent/US11444184B1

## CPC

- G01R 29/24: Arrangements for measuring quantities of charge
- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- H10D 48/3835: {Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)}
- H10D 30/402: {Single electron transistors; Coulomb blockade transistors}
- H10D 62/812: {Single quantum well structures}
- H10D 64/01: Manufacture or treatment
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method is disclosed, including positioning a lead wire of a gate chip at a distance of less than 10 nm from a semiconductor heterostructure. The heterostructure includes a surface layer and a subsurface layer. The method also includes inducing an electrostatic potential in the subsurface layer by applying a voltage to the lead wire. The method also includes loading a charge carrier into the subsurface layer. The method also includes detecting the charge carrier in the subsurface layer of the semiconductor heterostructure by emitting a radio-frequency pulse using a resonator coupled to the at least one lead wire of the gate chip, detecting a reflected pulse of the emitted radio-frequency pulse, and determining a phase shift of the reflected pulse relative to the emitted radio-frequency pulse. The method also includes characterizing the quantum dot by measuring valley splitting of the quantum dot.

## Claims

### Claim 1

A system, comprising:
a gate chip, comprising at least one lead wire; and
a semiconductor heterostructure, comprising a surface layer and at least one subsurface layer;
wherein the gate chip is configured to induce a quantum dot in the subsurface layer of the semiconductor heterostructure using the lead wire;
wherein inducing the quantum dot comprises inducing an electrostatic potential in the subsurface layer by applying a voltage to the lead wire such that the energy of a first excited orbital level of the induced quantum dot is larger than an effective temperature bath in the subsurface layer;
wherein the lead wire has a cross-sectional width between 5 nm and 30 nm;
wherein the gate chip is separated from the semiconductor heterostructure by a gap distance;
wherein the gap distance is less than 10 nm.

### Claim 2 (depends on 1)

The system in accordance with claim 1, wherein the voltage applied to the lead wire is between 0.01 V and 0.2 V.

### Claim 3 (depends on 1)

The system in accordance with claim 1, wherein inducing the quantum dot further comprises loading a charge carrier into the subsurface layer.

### Claim 4 (depends on 3)

The system in accordance with claim 3, wherein loading the charge carrier into the subsurface layer comprises creating a plurality of carriers in the semiconductor heterostructure by external excitation of photons with an energy greater than a bandgap energy of the semiconductor hetero structure.

### Claim 5 (depends on 3)

The system in accordance with claim 3, wherein loading the charge carrier into the subsurface layer comprises:
implanting a region of donors introducing doped regions of extra charge carriers into the semiconductor heterostructure; and
after the implanting, moving the lead wire of the gate chip near the doped regions to allow tunneling of the charge carrier into the quantum induced dot.

### Claim 6 (depends on 3)

The system in accordance with claim 3, wherein loading the charge carrier into the subsurface layer comprises:
implanting a region of donors introducing doped regions of extra charge carriers into the semiconductor heterostructure; and
creating a bath gate using one of the at least one lead wires to load charge carriers from the doped region into the induced quantum dot in the subsurface layer of the semiconductor heterostructure.

### Claim 7 (depends on 3)

The system in accordance with claim 3, wherein inducing the quantum dot further comprises detecting the charge carrier in the subsurface layer of the semiconductor heterostructure by:
emitting a radio-frequency pulse using a resonator coupled to the at least one lead wire of the gate chip;
detecting a reflected pulse of the emitted radio-frequency pulse; and
determining a phase shift of the reflected pulse relative to the emitted radio-frequency pulse.

### Claim 8 (depends on 7)

The system in accordance with claim 7, wherein the resonator has a Q factor of at least 103.

### Claim 9 (depends on 7)

The system in accordance with claim 7, wherein detecting the charge carrier further comprises characterizing the quantum dot by measuring valley splitting of the quantum dot.

### Claim 10 (depends on 7)

The system in accordance with claim 7, wherein the charge carrier comprises a single electron.

### Claim 11 (depends on 7)

The system in accordance with claim 7, wherein the charge carrier comprises two electrons.

### Claim 12 (depends on 7)

The system in accordance with claim 7, wherein the at least one lead wire comprises a plurality of lead wires, and wherein the gate chip is further configured to induce a plurality of quantum dots on the semiconductor heterostructure, adapted for use in a multiple quantum dot qubit quantum computer.

### Claim 13 (depends on 3)

The system in accordance with claim 3, wherein the charge carrier comprises a qubit.

### Claim 14 (depends on 1)

The system in accordance with claim 1, wherein the semiconductor heterostructure comprises an inversion layer.

### Claim 15 (depends on 14)

The system in accordance with claim 14, wherein the subsurface layer is one of:
silicon;
germanium;
a III-V semiconductor;
zinc oxide; and
topological material.

### Claim 16 (depends on 1)

The system in accordance with claim 1, wherein the semiconductor heterostructure comprises a quantum well.

### Claim 17 (depends on 1)

The system in accordance with claim 1, wherein the semiconductor heterostructure comprises a van der Waals heterostructure.