# US 11,444,183 B2 · Semiconductor structure and formation method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,183 B2
- Document ID: US11444183B2
- Status: Granted
- Kind: B2
- Application number: 17/092,566
- Filed: 2020-11-09
- Published: 2021-02-25
- Granted: 2022-09-13
- Earliest claimed: 2019-06-18
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Nan Wang
- Web page: https://patentgrep.com/patent/US11444183B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6518: {by introduction of substances into an already-existing insulating layer}
- H10P 14/6539: {by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions}
- H10P 30/40: into insulating materials
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate, wherein the substrate comprises a device region for forming a device and isolation regions located at both sides of the device region;
discrete fins, protruding from the substrate of the device region; and
isolation layers, located on the substrate exposed by the fins;
wherein the isolation layers cover part of the side walls of the fins, the isolation layers located in the isolation regions are regarded as target isolation layers, and surfaces of the target isolation layers are lower than surfaces of the isolation layers between the discrete fins, a height difference between the surfaces of the target isolation layers and the surfaces of the isolation layers between the discrete fins is greater than or equal to a height difference between a surface of the substrate of the isolation regions and a surface of the substrate of the device region.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the isolation layers between the isolation regions and edge fins are flush with the target isolation layers, and the edge fins are fins that are close to an edge of the device region.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein a height difference between the surfaces of the target isolation layers and the surfaces of the isolation layers between the discrete fins is 5 nm to 30 nm.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein a height difference between a surface of the substrate of the isolation regions and a surface of the substrate of the device region is 2 nm to 10 nm.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, further comprising a gate structure, spanning the fins and covering part of the top surfaces and part of the side walls of the fins.