# US 11,444,181 B2 · Source/drain formation with reduced selective loss defects

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- Number: US 11,444,181 B2
- Document ID: US11444181B2
- Status: Granted
- Kind: B2
- Application number: 17/157,444
- Filed: 2021-01-25
- Published: 2022-01-27
- Granted: 2022-09-13
- Earliest claimed: 2020-07-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chiang Chang; Ming-Hua Yu; Li-Li Su
- Web page: https://patentgrep.com/patent/US11444181B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0193: {the components including FinFETs}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/20: of semiconductor materials
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

## Claims

### Claim 1

A method comprising:
forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect Transistor (FinFET) region and a p-type FinFET region, respectively;
forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively;
forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin;
performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin;
removing the first epitaxy mask;
forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin;
performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin; and
removing the second epitaxy mask, wherein after the second epitaxy mask is removed, a first portion of the second epitaxy mask is left on the first dielectric fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the removing the first epitaxy mask, substantially no portion of the first epitaxy mask is left on the second dielectric fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein each of the first epitaxy mask and the second epitaxy mask has a thickness in a range between about 0.5 nm and about 2.5 nm.

### Claim 4 (depends on 1)

The method of claim 1 further comprising forming a third dielectric fin dividing the n-type FinFET region from the p-type FinFET region, wherein at a time after the second epitaxy mask is removed, a second portion of the second epitaxy mask is left on a first side of the third dielectric fin, with the first side facing the n-type FinFET region.

### Claim 5 (depends on 4)

The method of claim 4, wherein at the time, no portion of the first epitaxy mask and the second epitaxy mask is left on a second side of the third dielectric fin, with the second side facing the p-type FinFET region.

### Claim 6 (depends on 1)

The method of claim 1, wherein in the first epitaxy process, a portion of an n-type semiconductor material for forming the n-type epitaxy region is formed on a dielectric material in the p-type FinFET region as a defect, and during the second epitaxy process, the defect is removed.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second epitaxy mask and the first dielectric fin are formed of a same dielectric material.

### Claim 8 (depends on 7)

The method of claim 7, wherein both of the second epitaxy mask and the first dielectric fin comprise Si, O, C, and N.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second epitaxy mask and the first dielectric fin are formed of different dielectric materials.

### Claim 10

A structure comprising:
an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region;
an n-type FinFET in the n-type FinFET region, wherein the n-type FinFET comprises:
a first semiconductor fin;
a first gate stack on the first semiconductor fin; and
an n-type source/drain region aside the first gate stack;
a first dielectric fin in the n-type FinFET region, wherein the first dielectric fin has a first width;
a p-type FinFET in the p-type FinFET region, wherein the p-type FinFET comprises:
a second semiconductor fin;
a second gate stack on the second semiconductor fin; and
a p-type source/drain region aside the second gate stack; and
a second dielectric fin in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the first width is greater than the second width by a difference greater than about 1 nm.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the difference is in a range between about 1 nm and about 5 nm.

### Claim 13 (depends on 10)

The structure of claim 10, wherein the first dielectric fin comprises:
an inner portion formed of a first material; and
an outer portion on sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

### Claim 14 (depends on 13)

The structure of claim 13, wherein the second dielectric fin comprises the first material, and is free from the second material.

### Claim 15 (depends on 13)

The structure of claim 13, wherein the inner portion of the first dielectric fin comprises:
an upper portion;
a middle portion below the upper portion, wherein the middle portion is in physical contact with the n-type source/drain region; and
a lower portion below the middle portion, wherein the lower portion is free from the outer portion formed on its sidewall.

### Claim 16 (depends on 10)

The structure of claim 10, wherein the n-type source/drain region and the first dielectric fin have no fin located therebetween, and wherein the p-type source/drain region and the second dielectric fin have no fin located therebetween.

### Claim 17

A structure comprising:
a semiconductor substrate;
a plurality of isolation regions extending into the semiconductor substrate;
a first n-type source/drain region and a second n-type source/drain region extending higher than top surfaces of the plurality of isolation regions;
a first dielectric fin between the first n-type source/drain region and the second n-type source/drain region, wherein the first dielectric fin has a first width measured at a first level higher than the top surfaces of the plurality of isolation regions, and a second width measured at a second level lower than the top surfaces of the plurality of isolation regions;
a first p-type source/drain region and a second p-type source/drain region extending higher than the top surfaces of the plurality of isolation regions; and
a second dielectric fin between the first p-type source/drain region and the second p-type source/drain region, wherein the second dielectric fin has a third width measured at the first level, and a fourth width measured at the second level, and wherein the first width is greater than the third width.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the second width is substantially equal to the fourth width.

### Claim 19 (depends on 17)

The structure of claim 17, wherein the first dielectric fin contacts the first n-type source/drain region and the second n-type source/drain region, and an upper portion of the first dielectric fin has the first width, and a lower portion of the first dielectric fin is narrower than the upper portion.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the first dielectric fin comprises:
an inner portion formed of a first material; and
an outer portion on sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.