# US 11,444,179 B2 · Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

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- Number: US 11,444,179 B2
- Document ID: US11444179B2
- Status: Granted
- Kind: B2
- Application number: 16/953,598
- Filed: 2020-11-20
- Published: 2021-09-02
- Granted: 2022-09-13
- Earliest claimed: 2020-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Xusheng Wu; Chang-Miao Liu; Huiling Shang
- Web page: https://patentgrep.com/patent/US11444179B2

## CPC

- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1908: {using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 30/209: {in silicon to make buried insulating layers}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.

## Claims

### Claim 1

A method, comprising:
depositing a SiGe layer over a semiconductor layer;
depositing a Si layer over the SiGe layer, thereby forming a semiconductor substrate;
doping the SiGe layer with oxygen;
annealing the oxygen-doped SiGe layer, such that the semiconductor substrate includes an oxide layer embedded therein;
forming a multi-layer stack (ML) including alternating channel layers and non-channel layers over the semiconductor substrate;
forming an epitaxial S/D feature in the ML, wherein a bottom surface of the epitaxial S/D feature directly contacts the oxide layer;
and
subsequently forming a high-k metal gate stack (HKMG) over the ML and in place of the non-channel.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the oxygen-doped SiGe layer includes performing an oxygen implantation process.

### Claim 3 (depends on 1)

The method of claim 1, wherein annealing the oxygen-doped SiGe layer includes performing a laser anneal, a spike anneal, a thermal anneal, or combinations thereof.

### Claim 4 (depends on 1)

The method of claim 1, wherein the oxide layer is a first oxide layer, the method further comprising:
forming a second oxide layer over a top surface of the semiconductor layer before forming the oxygen-doped SiGe layer; and
subsequently removing the second oxide layer after annealing the oxygen-doped SiGe layer.

### Claim 5 (depends on 1)

The method of claim 1,
wherein the oxide layer includes silicon oxide, germanium oxide, or a combination thereof.

### Claim 6 (depends on 5)

The method of claim 5, wherein the oxide layer includes silicon oxide, germanium oxide, or a combination thereof.

### Claim 7 (depends on 5)

The method of claim 5, wherein the semiconductor layer includes elemental silicon, and wherein the silicon oxide includes SiOx, where 1≤x≤2.

### Claim 8

A method, comprising:
forming a semiconductor substrate, including:
providing a first semiconductor layer, wherein the first semiconductor layer includes elemental Si;
forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer includes SiGe;
forming a third semiconductor layer on the second semiconductor layer, thereby forming the semiconductor substrate, wherein the third semiconductor layer includes elemental Si;
performing an implantation process to dope the second semiconductor layer with oxygen; and
performing an annealing process to the doped second semiconductor layer to form an oxide layer;
forming a multi-layer structure (ML) including alternating Si layers and SiGe layers over the semiconductor substrate;
forming a placeholder gate stack over the ML;
forming a source/drain (S/D) recess in the ML, thereby exposing the oxide layer;
forming an S/D feature in the S/D recess; and
forming a metal gate stack in place of the placeholder gate stack and in place of the SiGe layers of the ML.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the second and the third semiconductor layers includes epitaxially growing the second and the third semiconductor layers.

### Claim 10 (depends on 8)

The method of claim 8, wherein annealing the doped second semiconductor layer includes performing a melting laser anneal process.

### Claim 11 (depends on 8)

The method of claim 8, wherein the oxide layer includes germanium oxide, silicon oxide, or a combination thereof.

### Claim 12 (depends on 8)

The method of claim 8, further comprising forming a protective layer over the third semiconductor layer before performing the implantation process and removing the protective layer after annealing the doped second semiconductor layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the protective layer includes oxidizing the third semiconductor layer to form silicon oxide.

### Claim 14 (depends on 8)

The method of claim 8, wherein annealing the doped second semiconductor layer includes applying oxygen and/or hydrogen while annealing.

### Claim 15

A semiconductor structure, comprising:
a semiconductor substrate;
an oxide layer disposed over the semiconductor substrate, wherein the oxide layer includes germanium;
a stack of semiconductor layers disposed over the oxide layer;
a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers; and
an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the semiconductor substrate includes elemental silicon but is free of oxygen, and wherein the oxide layer includes silicon and oxygen.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the first oxide layer includes SiO, SiO2, or a combination thereof.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein the oxide layer includes germanium oxide.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, wherein the semiconductor layers are first semiconductor layers, the semiconductor structure further comprising a second semiconductor layer disposed between the oxide layer and a bottom portion of the HKMG, wherein the first semiconductor layers and the second semiconductor layer have the same composition.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein the second semiconductor layer and the semiconductor substrate have the same composition.