# US 11,444,178 B2 · Inner spacer liner

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- Number: US 11,444,178 B2
- Document ID: US11444178B2
- Status: Granted
- Kind: B2
- Application number: 17/097,711
- Filed: 2020-11-13
- Published: 2022-05-19
- Granted: 2022-09-13
- Earliest claimed: 2020-11-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jin-Mu Yin; Wei-Yang Lee; Chih-Hao Yu; Yen-Ting Chen; Chia-Pin Lin
- Web page: https://patentgrep.com/patent/US11444178B2

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

## Claims

### Claim 1

A semiconductor device, comprising:
a first source/drain feature and a second source/drain feature over a substrate;
a plurality of channel members extending between the first source/drain feature and the second source/drain feature;
a plurality of inner spacer features interleaving the plurality of channel members;
a gate structure wrapping around each of the plurality of channel members; and
a semiconductor liner sandwiched directly between a sidewall of the gate structure and each of the plurality of inner spacer features.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor liner is sandwiched between each of the plurality of inner spacer features and an adjacent channel member of the plurality of channel members.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor liner comprises silicon (Si).

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first source/drain feature comprises silicon (Si) and an n-type dopant.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first source/drain feature comprises silicon germanium (SiGe) and a p-type dopant.

### Claim 6 (depends on 1)

The semiconductor device of claim 1,
wherein the first source/drain feature comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer,
wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant,
wherein a concentration of the dopant in the second epitaxial layer is greater than a concentration of the dopant in the first epitaxial layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first epitaxial layer is in contact with the semiconductor liner and the second epitaxial layer is spaced apart from the semiconductor liner.

### Claim 8

A semiconductor structure, comprising:
a first epitaxial feature and a second epitaxial feature;
a plurality of nanostructures extending between the first epitaxial feature and the second epitaxial feature along a first direction;
a plurality of inner spacer features interleaving the plurality of nanostructures;
a gate structure wrapping around each of the plurality of nanostructures; and
a silicon liner sandwiched directly between the gate structure and each of the plurality of inner spacer features along the first direction,
wherein the silicon liner is in contact with the first epitaxial feature and the second epitaxial feature.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the silicon liner is sandwiched between each of the plurality of inner spacer features and an adjacent nanostructure of the plurality of nanostructures.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the plurality of nanostructures are coupled together by the silicon liner.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8,
wherein the first epitaxial feature comprises a first epitaxial layer and a second epitaxial layer,
wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant,
wherein a concentration of the dopant in the second epitaxial layer is greater than a concentration of the dopant in the first epitaxial layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the first epitaxial layer is in contact with the silicon liner and the second epitaxial layer is spaced apart from the silicon liner.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11,
wherein the first epitaxial feature comprises silicon (Si),
wherein the dopant is an n-type dopant.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11,
wherein the first epitaxial feature comprises silicon germanium (SiGe),
wherein the dopant is a p-type dopant.

### Claim 15

A method, comprising:
forming a stack over a substrate, wherein the stack comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers;
forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure comprising a channel region and a source/drain region;
recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers;
selectively and partially recessing the plurality of silicon germanium layers to form a plurality of inner spacer recesses;
depositing a semiconductor layer over the plurality of inner spacer recesses;
depositing an inner spacer layer over the semiconductor layer;
etching back the semiconductor layer and the inner spacer layer to form a plurality of inner spacer features in the plurality of inner spacer recesses;
after the etching back, forming a source/drain feature in the source/drain trench;
releasing the plurality of silicon layers in the channel region as a plurality of channel members; and
forming a gate structure around each of the plurality of channel members.

### Claim 16 (depends on 15)

The method of claim 15, where the depositing of the semiconductor layer comprises epitaxially depositing a silicon layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein after the depositing of the semiconductor layer, the semiconductor layer in contact with the plurality of silicon germanium layers.

### Claim 18 (depends on 15)

The method of claim 15, wherein the forming of the source/drain feature comprises:
depositing a first epitaxial layer; and
depositing a second epitaxial layer over the first epitaxial layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the depositing of the first epitaxial layer comprises depositing the first epitaxial layer in contact with the silicon layers and the semiconductor layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second epitaxial layer is spaced apart from the semiconductor layer.