# US 11,444,177 B2 · Semiconductor device and method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,177 B2
- Document ID: US11444177B2
- Status: Granted
- Kind: B2
- Application number: 16/940,226
- Filed: 2020-07-27
- Published: 2021-08-05
- Granted: 2022-09-13
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wen-Kai Lin; Che-Hao Chang; Chi On Chui; Yung-Cheng Lu
- Web page: https://patentgrep.com/patent/US11444177B2

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a plurality of semiconductor channel structures over the substrate;
a gate structure over the plurality of semiconductor channel structures, wherein the gate structure extends between adjacent ones of the plurality of semiconductor channel structures;
a source/drain region adjacent the gate structure, the source/drain region contacting the plurality of semiconductor channel structures; and
an inner spacer interposed between the source/drain region and the gate structure, the inner spacer comprising:
a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer comprising silicon and nitrogen;
a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer comprising silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer; and
a third inner spacer layer contacting the second inner spacer layer and the source/drain region, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer comprise carbon, and wherein an atomic percentage of carbon in the first inner spacer layer is greater than an atomic percentage of carbon in the second inner spacer layer and the third inner spacer layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a first sidewall of the inner spacer contacts the source/drain region, the first sidewall having a W-shape in a cross-sectional view.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first inner spacer layer comprises silicon carbonitride, wherein the first inner spacer layer has an atomic percentage of carbon from 5 percent to 20 percent, and wherein the first inner spacer layer has an atomic percentage of nitrogen from 25 percent to 45 percent.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first inner spacer layer comprises silicon nitride, and wherein the first inner spacer layer has an atomic percentage of nitrogen from 35 percent to 50 percent.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second inner spacer layer comprises silicon oxycarbonitride, wherein the second inner spacer layer has an atomic percentage of oxygen from 25 percent to 60 percent, wherein the second inner spacer layer has an atomic percentage of carbon of less than 10 percent, and wherein the second inner spacer layer has an atomic percentage of nitrogen from 10 percent to 50 percent.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the second inner spacer layer comprises silicon oxynitride, wherein the second inner spacer layer has an atomic percentage of oxygen from 25 percent to 60 percent, and wherein the second inner spacer layer has an atomic percentage of nitrogen from 10 percent to 50 percent.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first inner spacer layer has a dielectric constant from 6.0 to 7.3, and wherein the second inner spacer layer has a dielectric constant from 4.2 to 6.0.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a thickness of the first inner spacer layer to a thickness of the second inner spacer layer is 4.5.

### Claim 9

A semiconductor device comprising:
a semiconductor substrate;
a plurality of channel regions over the semiconductor substrate;
a gate structure over the plurality of channel regions, wherein the gate structure extends between adjacent ones of the plurality of channel regions;
upper spacers along sidewalls of the gate structure;
a source/drain region adjacent the gate structure; and
a plurality of inner spacers, each of the inner spacers being interposed between the adjacent ones of the plurality of channel regions, each of the inner spacers being interposed between the source/drain region and the gate structure, each of the inner spacers comprising:
a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer comprising silicon and nitrogen;
a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer comprising silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer; and
a third inner spacer layer contacting the second inner spacer layer and the source/drain region, the third inner spacer layer comprising silicon and nitrogen, wherein sidewalls of the inner spacers adjacent the source/drain region are W-shaped in a cross-sectional view, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer comprise carbon, and wherein an atomic percentage of carbon in the first inner spacer layer is greater than an atomic percentage of carbon in the second inner spacer layer and the third inner spacer layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the third inner spacer layer comprises silicon, nitrogen, and oxygen, and wherein an atomic percentage of oxygen in the second inner spacer layer is greater than an atomic percentage of oxygen in the third inner spacer layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein a thickness of the inner spacers measured between the source/drain region and the gate structure is greater than 3 nm.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein sidewalls of the inner spacers are recessed from sidewalls of the plurality of channel regions less than 10 Å.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein a dielectric constant of the first inner spacer layer is from 6.0 to 7.3, wherein a dielectric constant of the second inner spacer layer is from 4.2 to 5.7, and wherein a dielectric constant of the third inner spacer layer is from 4.5 to 6.0.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein an atomic percentage of carbon in the first inner spacer layer is from 10 percent to 15 percent, wherein an atomic percentage of carbon in the second inner spacer layer is from 0 percent to 5 percent, and wherein an atomic percentage of carbon in the third inner spacer layer is from 3 percent to 10 percent.

### Claim 15

A method comprising:
forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material;
etching sidewalls of the first semiconductor material to form sidewall recesses;
depositing a first inner spacer layer over the multi-layer stack and in the sidewall recesses;
depositing a second inner spacer layer over the first inner spacer layer;
depositing a third inner spacer layer filling the sidewall recesses;
performing a first etch process to etch the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer and form inner spacers comprising remaining portions of the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer in the sidewall recesses, wherein the first etch process etches the second inner spacer layer at an etching rate greater than an etching rate of the third inner spacer layer;
performing a second etch process to remove the first semiconductor material and form first recesses extending between the inner spacers, wherein the second etch process etches the first inner spacer layer at an etching rate less than an etching rate of the first semiconductor material; and
forming gate structures in the first recesses.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited in situ.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer are deposited at a temperature from 500° C. to 680° C.

### Claim 18 (depends on 15)

The method of claim 15, wherein a ratio of the etching rate of the first semiconductor material to the etching rate of the first inner spacer layer during the second etch process is from 50 to 500.

### Claim 19 (depends on 15)

The method of claim 15, wherein a ratio of the etching rate of the second inner spacer layer to the etching rate of the third inner spacer layer during the first etch process is from 1.2 to 3.0.

### Claim 20 (depends on 19)

The method of claim 19, wherein a ratio of an etching rate of the second inner spacer layer to the etching rate of the first inner spacer layer during the first etch process is from 1.2 to 3.0.