# US 11,444,176 B2 · Structure and formation method of semiconductor device structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,176 B2 - Document ID: US11444176B2 - Status: Granted - Kind: B2 - Application number: 16/505,917 - Filed: 2019-07-09 - Published: 2019-10-31 - Granted: 2022-09-13 - Earliest claimed: 2015-05-22 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Po-Chi Wu; Chai-Wei Chang; Kuo-Hui Chang; Yi-Cheng Chao - Web page: https://patentgrep.com/patent/US11444176B2 ## CPC - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers} - H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack. ## Claims ### Claim 1 A semiconductor device, comprising: a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the sidewalls of the conductive fill layer extending from the bottommost surface of the conductive fill layer to the topmost surface of the conductive fill layer, an entirety of each of the sidewalls of the conductive fill layer being a planar sidewall; a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the conductive fill layer, the cap element having a first width near the gate stack and a second width near an upper portion of the cap element, the second width being greater than the first width, a portion of the conductive fill layer extending above a bottommost surface of the cap element; a spacer element extending along a sidewall of the cap element and a sidewall of the gate stack, the spacer element having an inner sidewall closest to the sidewall of the gate stack, the inner sidewall having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the inner sidewall extending from the lower portion of the inner sidewall to a topmost surface of the spacer element, an interface between the lower portion and the upper portion being above the topmost surface of the conductive fill layer, wherein the gate stack further comprises a gate dielectric layer, a first portion of the gate dielectric layer being interposed between the work function layer and the semiconductor substrate, a second portion of the gate dielectric layer being interposed between the work function layer and the spacer element, the topmost surface of the conductive fill layer being above a topmost surface of the gate dielectric layer, the topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer; and a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the spacer element. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the gate dielectric layer comprises hafnium oxide. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the work function layer comprises a metal nitride, a metal carbide, or an aluminide. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the metal nitride comprises titanium nitride or tantalum nitride. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the conductive fill layer comprises tungsten. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the upper portion of the inner sidewall and an imaginary plane extending from the lower portion of the inner sidewall towards a topmost surface of the cap element form an angle, and wherein the angle is in a range from about 1 degree to about 10 degrees. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the lower portion of the inner sidewall and a top surface of the semiconductor substrate form an angle, and wherein the angle is in a range from about 85 degrees to about 95 degrees. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the dielectric material of the cap element is in physical contact with the spacer element. ### Claim 9 A semiconductor device, comprising: a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the conductive fill layer being surrounded by the work function layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the conductive fill layer having a sidewall extending from the topmost surface of the work function layer to the topmost surface of the conductive fill layer, an entirety of the sidewall of the conductive fill layer being a planar sidewall, wherein the gate stack further comprises a gate dielectric layer, the gate dielectric layer surrounding the work function layer, a topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer; a cap element over the gate stack, a portion of the cap element extending below the topmost surface of the conductive fill layer, the portion of the cap element comprising a dielectric material, a sidewall of the cap element having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the sidewall of the cap element extending from the lower portion of the sidewall of the cap element to a topmost surface of the cap element; a spacer element having a first portion extending along a sidewall of the gate stack and a second portion extending along the sidewall of the cap element, the first portion of the spacer element having a first width, the second portion of the spacer element having a second width, the first width being greater than the second width; and a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the work function layer. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a width of the cap element at the topmost surface of the conductive fill layer is in a range from about 25 nm to about 35 nm. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein a width of the cap element at the topmost surface of the cap element is in a range from about 27 nm to about 37 nm. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein the cap element comprises silicon nitride or silicon oxynitride. ### Claim 13 (depends on 9) The semiconductor device of claim 9, wherein the spacer element comprises silicon nitride, silicon oxynitride, or silicon oxide. ### Claim 14 (depends on 9) The semiconductor device of claim 9, wherein the cap element is in physical contact with the topmost surface of the gate dielectric layer and the topmost surface of the work function layer. ### Claim 15 A semiconductor device, comprising: a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the conductive fill layer having a uniform width as the conductive fill layer extends away from the topmost surface of the work function layer and toward the topmost surface of the conductive fill layer; a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the work function layer, a width of the cap element increasing as the cap element extends away from the topmost surface of the conductive fill layer and toward a topmost surface of the cap element; a spacer element on a sidewall of the cap element and a sidewall of the gate stack, the spacer element having an inner sidewall facing the sidewall of the gate stack and the sidewall of the cap element, the inner sidewall having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the inner sidewall extending from the lower portion of the inner sidewall to a topmost surface of the spacer element, at least a portion of the lower portion being above the topmost surface of the conductive fill layer, wherein the gate stack further comprises a gate dielectric layer, a portion of the gate dielectric layer extending along the inner sidewall of the spacer element, the topmost surface of the conductive fill layer being above a topmost surface of the gate dielectric layer, the topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer; and a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a top surface of the semiconductor substrate. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the topmost surface of the cap element is level with the topmost surface of the spacer element. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein a width of the gate stack is in a range from about 25 nm to about 35 nm. ### Claim 18 (depends on 15) The semiconductor device of claim 15, further comprising a dielectric layer extending along an outer sidewall of the spacer element, the outer sidewall of the spacer element being opposite to the inner sidewall of the spacer element. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein a topmost surface of the dielectric layer is level with the topmost surface of the cap element. ### Claim 20 (depends on 15) The semiconductor device of claim 15, wherein the cap element and the spacer element comprise silicon nitride.