# US 11,444,175 B2 · Fabrication of long gate devices

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- Number: US 11,444,175 B2
- Document ID: US11444175B2
- Status: Granted
- Kind: B2
- Application number: 17/008,045
- Filed: 2020-08-31
- Published: 2022-03-03
- Granted: 2022-09-13
- Earliest claimed: 2020-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sung-Hsin Yang; Jung-Chi Jeng; Ru-Shang Hsiao
- Web page: https://patentgrep.com/patent/US11444175B2

## CPC

- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/834: {comprising FinFETs}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 95/08: {Planarisation of organic insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

## Claims

### Claim 1

A method, comprising:
providing a workpiece including:
a first dummy gate stack and a second dummy gate stack disposed in a first area of the workpiece,
a first source/drain feature disposed between the first dummy gate stack and the second dummy gate stack,
a third dummy gate stack and a fourth dummy gate stack disposed in a second area of the workpiece,
a second source/drain feature disposed between the third dummy gate stack and the fourth dummy gate stack,
a hard mask layer disposed over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack;
depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and
selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack,
wherein the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack comprise polysilicon.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first PR layer portion includes a first thickness and the second PR layer portion includes a second thickness greater than the first thickness.

### Claim 3 (depends on 1)

The method of claim 1, wherein a difference between a thickness of the first PR layer portion and a thickness of the second PR layer portion is between about 100 Å and about 300 Å.

### Claim 4 (depends on 1)

The method of claim 1,
wherein a first width of the first dummy gate stack is substantially equal to a second width of the second dummy gate stack,
wherein a third width of the third dummy gate stack is between about 240 nm and 1800 nm.

### Claim 5 (depends on 4)

The method of claim 4,
wherein the selectively forming of the first opening and the second opening comprises use of a lithography radiation source,
wherein a fourth width of the fourth dummy gate stack is substantially equal to a wavelength of the lithography radiation source.

### Claim 6 (depends on 5)

The method of claim 5, wherein the wavelength is about 248 nm.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
etching back the first PR layer portion and the second PR layer portion;
removing the hard mask layer;
depositing a dielectric layer over the workpiece;
planarizing the workpiece such that top surfaces of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack, and the dielectric layer are coplanar; and
replacing the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack with a first gate structure, a first isolation gate structure, a second gate structure, and a second isolation gate structure, respectively.

### Claim 8

A method, comprising:
providing a workpiece, the workpiece comprising:
a plurality of fin structures extending along a first direction over a first area and a second area of the workpiece,
a plurality of first dummy gate stacks and a plurality of second dummy gate stacks disposed in the first area,
a plurality of third dummy gate stack and a plurality of fourth dummy gate stacks disposed in the second area,
a hard mask layer disposed over each of the plurality of first dummy gate stacks, the plurality of second dummy gate stacks, the plurality of third dummy gate stacks, and the plurality of fourth dummy gate stacks;
depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and
selectively forming a plurality of first openings through the second PR layer portion over the plurality of third dummy gate stack and a plurality of second openings through the second PR layer portion over the plurality of fourth dummy gate stacks, while the first PR layer portion remains intact.

### Claim 9 (depends on 8)

The method of claim 8,
wherein the plurality of first dummy gate stacks and the plurality of second dummy gate stacks comprise a first dummy gate stack density,
wherein the plurality of third dummy gate stacks and the plurality of fourth dummy gate stacks comprise a second dummy gate stack density greater than the first dummy gate stack density.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first PR layer portion includes a first thickness and the second PR layer portion includes a second thickness greater than the first thickness.

### Claim 11 (depends on 10)

The method of claim 10, wherein a difference between the first thickness and the second thickness is between about 100 Å and about 300 Å.

### Claim 12 (depends on 8)

The method of claim 8,
wherein the plurality of first dummy gate stacks are spaced apart from one another by at least one of the plurality of second dummy gate stacks,
wherein the plurality of third dummy gate stacks are spaced apart from one another by at least one of the plurality of fourth dummy gate stacks.

### Claim 13 (depends on 8)

The method of claim 8,
wherein a first width of each of the plurality of third dummy gate stacks is between about 240 nm and 1800 nm,
wherein the selectively forming of the plurality of first openings and the plurality of second openings comprises use of a lithography radiation source,
wherein a second width of the each of the plurality of fourth dummy gate stacks is substantially equal to a wavelength of the lithography radiation source.

### Claim 14 (depends on 13)

The method of claim 13, wherein the wavelength is about 248 nm.

### Claim 15 (depends on 8)

The method of claim 8, further comprising:
etching back the first PR layer portion and the second PR layer portion;
removing the hard mask layer over the workpiece;
depositing a dielectric layer over the workpiece;
planarizing the workpiece such that top surfaces of the plurality of first dummy gate stacks, the plurality of second dummy gate stacks, the plurality of third dummy gate stacks, and the plurality of fourth dummy gate stacks, and the dielectric layer are coplanar; and
replacing the plurality of first dummy gate stacks, the plurality of second dummy gate stacks, the plurality of third dummy gate stacks, and the plurality of fourth dummy gate stacks with a plurality of first gate structures, a plurality of first isolation gate structures, a plurality of second gate structures, and a plurality of second isolation gate structures, respectively.

### Claim 16

A method, comprising:
providing a workpiece comprising;
a first area having a first dummy gate stack density, the first area including a plurality of first dummy gate stacks and a plurality of second dummy gate stacks, and
a second area having second dummy gate stack density greater than the first dummy gate stack density, the second area including a plurality of third dummy gate stacks and a plurality of fourth dummy gate stacks;
depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area;
forming a plurality of openings through the second PR layer portion while the first PR layer portion remains intact; and
after the forming of the plurality of openings, etching back the PR layer,
wherein a gate length of each of the plurality of third dummy gate stacks is greater than a gate length of each of the plurality of first dummy gate stacks.

### Claim 17 (depends on 16)

The method of claim 16,
wherein the plurality of openings expose a portion of each of the plurality of third dummy gate stacks and each of the plurality of fourth dummy gate stacks,
wherein a gate length of each of the plurality of fourth dummy gate stacks is greater than a gate length of each of the plurality of second dummy gate stacks.

### Claim 18 (depends on 16)

The method of claim 16,
wherein the forming of the plurality of openings comprises use of a photolithography radiation source,
wherein a width of each of the plurality of first dummy gate stacks is greater than a wavelength of the photolithography radiation source,
wherein a width of each of the plurality of second dummy gate stacks is substantially equal to a wavelength of the photolithography radiation source.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first PR layer portion includes a first thickness and the second PR layer portion includes a second thickness greater than the first thickness.

### Claim 20 (depends on 19)

The method of claim 19, wherein a difference between the first thickness and the second thickness is between about 100 Å and about 300 Å.