# US 11,444,173 B2 · Semiconductor device structure with salicide layer and method for forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,173 B2
- Document ID: US11444173B2
- Status: Granted
- Kind: B2
- Application number: 15/797,973
- Filed: 2017-10-30
- Published: 2019-05-02
- Granted: 2022-09-13
- Earliest claimed: 2017-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsiang-Ku Shen; Jin-Mu Yin; Tsung-Chieh Hsiao; Chia-Lin Chuang; Li-Zhen Yu; Dian-Hau Chen; Shih-Wei Wang; De-Wei Yu; Chien-Hao Chen; Bo-Cyuan Lu; Jr-Hung Li; Chi-On Chui; Min-Hsiu Hung; Hung-Yi Huang; Chun-Cheng Chou; Ying-Liang Chuang; Yen-Chun Huang; Chih-Tang Peng; Cheng-Po Chau; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US11444173B2

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/082: {the openings being tapered via holes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
forming a fin structure over a substrate;
forming an isolation feature surrounding the fin structure;
after forming the isolation feature, forming a gate structure over the fin structure;
after forming the gate structure, forming fin spacers over sidewalls of the fin structure and an upper surface of the isolation feature;
removing a portion of the fin structure to form a recess extending between the fin spacers;
after forming the gate structure, forming gate spacers over sidewalls of the gate structure;
forming a source/drain structure over the fin structure, wherein the source/drain structure includes a bottom portion in the recess and an upper portion protruding from the recess and wider than the bottom portion, the upper portion of the source/drain structure overlaps the fin spacers, and a surface of the upper portion of the source/drain structure extending from one of the fin spacers to another one of the fin spacers has a curved profile;
depositing a dummy material layer to cover the source/drain structure;
removing the dummy material layer to expose the source/drain structure and the fin spacers;
forming a salicide layer over the source/drain structure and the fin spacers, wherein a bottom portion of the salicide layer extends below the upper portion of the source/drain structure;
forming a capping layer to cover sidewalls of the fin spacers and the salicide wherein a portion of the capping layer directly below the bottom portion of the salicide layer is in contact with a sidewall of one of the fin spacers;
depositing a dielectric layer to cover the capping layer, wherein the dielectric layer is made of a different material than the capping layer;
etching the dielectric layer to form a trench exposing the salicide layer; and
forming a contact over the salicide layer and in the trench,
wherein the dummy material layer comprises Ge, amorphous silicon or spin-on carbon, and a first interface between the salicide layer and one of the fin spacers is higher than a second interface between the source/drain structure and the fin structure.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein a portion of the salicide layer is etched during the formation of the trench.

### Claim 3 (depends on 1)

The method as claimed in claim 1, further comprising:
depositing a metal layer over the source/drain structure and the fin spacers;
performing an anneal process to form the salicide layer over the source/drain structure; and
removing the metal layer over the fin spacers.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the dummy material layer is removed by performing a dry etching process, and the dry etching process is performed by using an etchant comprising tetrafluoromethane, fluoromethane or hexa-fluoro-butadiene.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein after the salicide layer is formed, the salicide layer adjoins the fin spacers.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein a portion of the salicide layer extends onto sidewalls of the fin spacers and is not in direct contact with the contact.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein a bottom portion of the source/drain structure is sandwiched between of the fin spacers.

### Claim 8

A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate;
forming an isolation feature to surround a lower portion of the first fin structure and a lower portion of the second fin structure;
after forming the isolation feature, forming a gate structure across the first fin structure and the second fin structure;
after forming the gate structure, forming a first fin spacer, a second fin spacer, a third spacer and a fourth spacer over the isolation feature, wherein an upper portion of the first fin structure is sandwiched between the first fin spacer and the second fin spacer, and an upper portion of the second fin structure is sandwiched between the third fin spacer and the fourth fin spacer;
after forming the gate structure, forming gate spacers over sidewalls of the gate structure;
removing the upper portion of the first fin structure to form a first recess extending between the first fin spacer and the second fin spacer and removing the upper portion of the second fin structure to form a second recess extending between the third fin spacer and the fourth fin spacer;
forming a source/drain structure over the first fin structure and the second fin structure and adjacent to the gate structure, wherein the source/drain structure includes a first bottom portion in the first recess, a second bottom portion in the second recess, and an upper portion protruding from the first recess and the second recess and wider than the first bottom portion and the second bottom portion;
forming a sacrificial liner over the source/drain structure;
forming a dummy material layer to cover the sacrificial liner, wherein the sacrificial liner is made of a different material than the dummy material layer;
replacing the gate structure by a metal gate structure after the dummy material layer is formed;
forming a mask structure over a top surface of the metal gate structure;
removing the dummy material layer to expose the source/drain structure;
forming a metal layer over the gate spacers and the source/drain structure, wherein the metal layer contacts a sidewall of the mask structure;
forming a salicide layer covering the source/drain structure, wherein the salicide layer extends continuously from the first fin spacer to the fourth fin spacer, and a bottom portion of the salicide layer extends below the upper portion of the source/drain structure;
forming a capping layer over the salicide layer, wherein a portion of the capping layer directly below the bottom portion of the salicide layer is in contact with a sidewall of the first fin spacer;
forming a dielectric layer to cover the capping layer, wherein the dielectric layer is made of a different material than the capping layer;
etching the dielectric layer to form a trench exposing the salicide layer; and
forming a contact in the trench.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein a portion of the salicide layer is not in direct contact with the contact.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein forming a salicide layer further comprising:
performing an anneal process to form the salicide layer over the source/drain structure.

### Claim 11 (depends on 10)

The method as claimed in claim 10, further comprising:
removing the metal layer over the gate spacers after the salicide layer is formed.

### Claim 12 (depends on 8)

The method as claimed in claim 8, wherein the source/drain structure covers both the first fin structure and the second fin structure.

### Claim 13 (depends on 8)

The method as claimed in claim 8, further comprising:
removing the mask structure after forming the dielectric layer over the salicide layer.

### Claim 14

A method for forming a semiconductor device structure, comprising:
forming a fin structure and an isolation feature over a substrate, wherein a lower portion of the fin structure is embedded in the isolation feature;
forming a first gate structure over the fin structure;
after forming the first gate structure, forming fin spacers on the isolation feature and surrounding an upper portion of the fin structure;
removing a portion of the fin structure to form a recess extending between the fin spacers;
forming a source/drain structure from the recess, wherein the source/drain structure includes a bottom portion in the recess and an upper portion protruding from the recess and wider than the bottom portion;
forming a sacrificial material layer to cover the source/drain structure;
replacing the first gate structure with a second gate structure;
removing the sacrificial material layer to expose the source/drain structure;
forming a salicide layer along the source/drain structure, wherein a bottom portion of the salicide layer extends below the upper portion of the source/drain structure;
forming a capping layer over the salicide layer, wherein a portion of the capping layer directly below the bottom portion of the salicide layer is in contact with a sidewall of one of the fin spacers;
forming a dielectric layer to cover the capping layer, wherein the dielectric layer is made of a different material than the capping layer; and
forming a contact through the dielectric layer to land on the salicide layer.

### Claim 15 (depends on 14)

The method as claimed in claim 14, further comprising:
forming a gate spacer along a sidewall of the first gate structure, wherein the sacrificial material layer is removed to expose the gate spacer.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein forming the salicide layer over the fin structure comprises:
depositing a metal layer along the gate spacer and the source/drain structure;
reacting a first portion of the metal layer with the source/drain structure to form the salicide layer; and
removing a second portion of the metal layer from the gate spacer.

### Claim 17 (depends on 15)

The method as claimed in claim 15, further comprising:
forming a sacrificial liner along the source/drain structure and the gate spacer, wherein the sacrificial material layer is formed over the sacrificial liner,
wherein removing the sacrificial material layer comprises removing the sacrificial liner.

### Claim 18 (depends on 14)

The method as claimed in claim 14, wherein the salicide layer contacts at least one of the fin spacers.

### Claim 19 (depends on 14)

The method as claimed in claim 14, wherein:
forming the fin structure over the substrate comprises forming a first fin structure and a second fin structure;
the source/drain structure has a first surface extending outwardly from a first sidewall of the first fin structure to a second sidewall of the second fin structure.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein the salicide layer has a second surface extending outwardly from the first sidewall of the first fin structure to the second sidewall of the second fin structure.