# US 11,444,171 B2 · Self-aligned gate endcap (SAGE) architecture having gate or contact plugs

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- Number: US 11,444,171 B2
- Document ID: US11444171B2
- Status: Granted
- Kind: B2
- Application number: 16/294,307
- Filed: 2019-03-06
- Published: 2020-09-10
- Granted: 2022-09-13
- Earliest claimed: 2019-03-06
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Sairam Subramanian; Walid M. Hafez
- Web page: https://patentgrep.com/patent/US11444171B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first gate structure over a first semiconductor fin;
a second gate structure over a second semiconductor fin;
a gate endcap isolation structure between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures;
a gate plug over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure; and
a crystalline metal oxide material laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the crystalline metal oxide material comprises titanium and oxygen.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the crystalline metal oxide material is conductive.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the crystalline metal oxide material is at least partially polycrystalline or microcrystalline.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second gate structures each comprises an upper local gate contact and a lower gate electrode, and wherein the crystalline metal oxide material is further vertically between the upper local gate contact and the lower gate electrode.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate plug is vertically misaligned with the gate endcap isolation structure.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate plug has a width greater than a width of the gate endcap isolation structure.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a first trench contact structure over the first semiconductor fin;
a second trench contact structure over the second semiconductor fin, the gate endcap isolation structure laterally between the first trench contact structure and the second trench contact structure;
a trench contact plug over the gate endcap isolation structure and laterally between the first and second trench contact structures; and
a second crystalline metal oxide material laterally between and in contact with the trench contact plug and the first gate structure, and laterally between and in contact with the trench contact plug and the second gate structure.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second semiconductor fins protrude through a trench isolation region above a substrate, and wherein the gate endcap isolation structure is on the trench isolation region.

### Claim 10

An integrated circuit structure, comprising:
a first trench contact structure over a first semiconductor fin;
a second trench contact structure over a second semiconductor fin;
a gate endcap isolation structure between the first and second semiconductor fins and laterally between and in contact with the first and second trench contact structures;
a trench contact plug over the gate endcap isolation structure and laterally between the first trench contact structure and the second trench contact structure; and
a crystalline metal oxide material laterally between and in contact with the trench contact plug and the first trench contact structure, and laterally between and in contact with the trench contact plug and the second trench contact structure.

### Claim 11 (depends on 10)

The integrated circuit structure of claim 10, wherein the crystalline metal oxide material comprises titanium and oxygen.

### Claim 12 (depends on 10)

The integrated circuit structure of claim 10, wherein the crystalline metal oxide material is conductive.

### Claim 13 (depends on 10)

The integrated circuit structure of claim 10, wherein the crystalline metal oxide material is at least partially polycrystalline or microcrystalline.

### Claim 14 (depends on 10)

The integrated circuit structure of claim 10, wherein the first and second trench contact structures each comprises an upper portion and a lower portion, and wherein the crystalline metal oxide material is further vertically between the upper portion and the lower portion.

### Claim 15 (depends on 10)

The integrated circuit structure of claim 10, wherein the trench contact plug is vertically misaligned with the gate endcap isolation structure.

### Claim 16 (depends on 10)

The integrated circuit structure of claim 10, wherein the trench contact plug has a width greater than a width of the gate endcap isolation structure.

### Claim 17 (depends on 10)

The integrated circuit structure of claim 10, wherein the first and second semiconductor fins protrude through a trench isolation region above a substrate, and wherein the gate endcap isolation structure is on the trench isolation region.

### Claim 18

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first gate structure over a first semiconductor fin;
a second gate structure over a second semiconductor fin;
a gate endcap isolation structure between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures;
a gate plug over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure; and
a crystalline metal oxide material laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

### Claim 19 (depends on 18)

The computing device of claim 18, further comprising:
a memory coupled to the board.

### Claim 20 (depends on 18)

The computing device of claim 18, further comprising:
a communication chip coupled to the board.

### Claim 21 (depends on 18)

The computing device of claim 18, further comprising:
a camera coupled to the board.

### Claim 22 (depends on 18)

The computing device of claim 18, further comprising:
a battery coupled to the board.

### Claim 23 (depends on 18)

The computing device of claim 18, further comprising:
an antenna coupled to the board.

### Claim 24 (depends on 18)

The computing device of claim 18, wherein the component is a packaged integrated circuit die.