# US 11,444,170 B1 · Semiconductor device with backside self-aligned power rail and methods of forming the same

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- Number: US 11,444,170 B1
- Document ID: US11444170B1
- Status: Granted
- Kind: B1
- Application number: 17/199,629
- Filed: 2021-03-12
- Published: 2022-09-15
- Granted: 2022-09-13
- Earliest claimed: 2021-03-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chao Chou; Kuo-Cheng Chiang; Shi Ning Ju; Wen-Ting Lan; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US11444170B1

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

## Claims

### Claim 1

A semiconductor device comprising:
a dielectric layer formed over a conductive feature;
a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other;
a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and
a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a power rail formed below the conductive feature, wherein the power rail electrically contacts the first epitaxial feature via the conductive feature.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a second epitaxial feature disposed over a second source/drain region of the semiconductor stack, wherein a bottom surface of the second epitaxial feature is over a top surface of the dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an isolation feature disposed along sidewalls of the conductive feature and separating active regions of the semiconductor device.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the dielectric layer is about 6 nm to about 20 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a width of a contact portion between the conductive feature and the first epitaxial feature is more than about 10 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first epitaxial feature includes a silicide layer formed at a bottom surface of the first epitaxial feature contacting the conductive feature.

### Claim 8

A method of forming a semiconductor device, comprising:
forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a sacrificial layer, and first semiconductor layers and second semiconductor layers alternately stacked up over the sacrificial layer, and each of a material of the first semiconductor layers, a material of the second semiconductor layers, and a material of the sacrificial layer provides a different etching selectivity;
forming a first dummy gate structure and a second dummy gate structure over the semiconductor stack;
forming a first source/drain (S/D) trench between the first dummy gate structure and the second dummy gate structure, wherein the first S/D trench extends below the sacrificial layer;
replacing the sacrificial layer with a dielectric layer; and
epitaxially growing a first epitaxial feature in the first S/D trench, wherein a bottom portion of the first epitaxial feature separates the dielectric layer between the first dummy gate structure and the second dummy gate structure.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
forming an isolation feature around a lower portion of the semiconductor stack to isolate active regions of the semiconductor device;
selectively removing the second semiconductor layers;
replacing the first dummy gate structure with a first metal gate structure and replacing the second dummy gate structure a second metal gate structure, wherein the first metal gate structure and the second metal gate structure wrap each of the first semiconductor layers;
removing the substrate and the lower portion of the semiconductor stack to form an opening in the isolation feature, wherein the dielectric layer and the bottom portion of the first epitaxial feature are exposed from the opening; and
forming a conductive feature below the dielectric layer and the bottom portion of the first epitaxial feature in the opening.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a power rail below and contacting the conductive feature.

### Claim 11 (depends on 9)

The method of claim 9, wherein a top surface of the isolation feature is below a bottom surface of the sacrificial layer.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
depositing an etch stop layer (ESL) in the substrate below the sacrificial layer, wherein the ESL separates the substrate to a first portion above the ESL and below the isolation feature and a second portion below the ESL;
wherein the removing the substrate and the lower portion of the semiconductor stack includes:
removing the second portion of the substrate to expose the ESL;
selectively removing the ESL;
removing the first portion of the substrate to expose the isolation feature; and
selectively removing the lower portion of the semiconductor stack to form the opening in the isolation feature.

### Claim 13 (depends on 8)

The method of claim 8, wherein the forming the first S/D trench between the first dummy gate structure and the second dummy gate structure includes:
removing a portion of the semiconductor stack along sidewalls of the first dummy gate structure and the second dummy gate structure to form a first S/D trench between the first dummy gate structure and the second dummy gate structure; and
further recessing the first S/D trench such that a bottom surface of the first S/D trench is below a bottom surface of the sacrificial layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
removing a portion of the semiconductor stack along a sidewall of the second dummy gate structure away from the first dummy gate structure to form a second S/D trench, wherein a bottom surface of the second S/D trench is above a top surface of the sacrificial layer; and
epitaxially growing a second epitaxial feature in the second S/D trench, wherein a bottom surface of the second epitaxial feature is above a top surface of the sacrificial layer.

### Claim 15 (depends on 8)

The method of claim 8, wherein the replacing the sacrificial layer with the dielectric layer includes:
selectively removing the sacrificial layer from the first S/D trench to form a gap;
depositing a dielectric material in the gap; and
removing a portion of the dielectric material in the first S/D trench such that the first S/D trench extending through the dielectric material.

### Claim 16

A method of forming a semiconductor device, comprising:
forming a sacrificial layer over a substrate;
alternately depositing first semiconductor layers and second semiconductor layers over the sacrificial layer, wherein each of a material of the first semiconductor layers, a material of the second semiconductor layers, and a material of the sacrificial layer provides a different etching selectivity;
patterning the first semiconductor layers, the second semiconductor layers, the sacrificial layer, and a top portion of the substrate to form a semiconductor stack;
forming a first dummy gate structure and a second dummy gate structure over the semiconductor stack;
etching along sidewalls of the first dummy gate structure and the second dummy gate structure to form a first source/drain (S/D) trench between the first dummy gate structure and the second dummy gate structure, and a second S/D trench along a sidewall of the second dummy gate structure away from the first dummy gate structure, wherein bottom surfaces of the first S/D trench and the second S/D trench are above the sacrificial layer;
further etching the first S/D trench such that the bottom surface of the first S/D trench is below a bottom surface of the sacrificial layer, while keeping the second S/D trench unchanged;
replacing the sacrificial layer with a dielectric layer; and
epitaxially growing a first epitaxial feature in the first S/D trench and a second epitaxial feature in the second S/D trench.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
selectively removing the second semiconductor layers;
replacing the first dummy gate structure with a first metal gate structure and replacing the second dummy gate structure a second metal gate structure, wherein the first and second metal gate structures wrap each of the first semiconductor layers;
removing the substrate to expose the first epitaxial feature and the dielectric layer; and
forming a conductive feature contacting the dielectric layer and the first epitaxial feature.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming an isolation feature around a lower portion of the semiconductor stack, wherein a top surface of the isolation feature is below a bottom surface of the sacrificial layer;
wherein the removing the substrate includes:
removing a bottom portion of the substrate to expose the isolation feature; and
removing the top portion of the substrate to form an opening in the isolation feature to expose the first epitaxial feature and the dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein the further etching the first S/D trench includes:
forming a patterned photoresist layer over the first dummy gate structure and the second dummy gate structure, wherein the patterned photoresist layer exposes the first S/D trench; and
removing a portion of the sacrificial layer between the first dummy gate structure and the second dummy gate structure through the patterned photoresist layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein a width of a removed portion of the sacrificial layer is more than about 10 nm.