# US 11,444,168 B2 · Transistor devices and methods of forming transistor devices

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- Number: US 11,444,168 B2
- Document ID: US11444168B2
- Status: Granted
- Kind: B2
- Application number: 17/086,501
- Filed: 2020-11-02
- Published: 2022-05-05
- Granted: 2022-09-13
- Earliest claimed: 2020-11-02
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Jiacheng Lei; James Jerry Joseph; Khee Yong Lim; Lulu Peng; Lawrence Selvaraj Susai
- Web page: https://patentgrep.com/patent/US11444168B2

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 64/01: Manufacture or treatment
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

## Claims

### Claim 1

A transistor device comprising:
a substrate;
a buffer layer arranged over the substrate;
a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; wherein the gate terminal is arranged laterally between the source terminal and the drain terminal, wherein the source terminal and the drain terminal are arranged directly on the buffer layer;
a barrier layer arranged over the buffer layer, wherein the harrier layer is disposed laterally between the source terminal and the drain terminal and wherein the barrier layer comprises a recess laterally between the gate terminal and the drain terminal;
a passivation layer arranged over the barrier layer, wherein a part of the gate terminal is arranged over the passivation layer, and wherein the passivation layer extends into the recess of the barrier layer overlapping vertically and horizontally with the barrier laver, and
a gate dielectric layer arranged over the passivation layer, the gate dielectric layer overlapping vertically and horizontally with the passivation layer, wherein the gate dielectric layer and the passivation layer are made of different materials.

### Claim 2 (depends on 1)

The transistor device of claim 1, wherein the part of the gate terminal is arranged over the recess of the barrier layer.

### Claim 3 (depends on 1)

The transistor device of claim 1, wherein the recess extends partially through a thickness of the barrier layer.

### Claim 4 (depends on 1)

The transistor device of claim 1, wherein the recess extends fully through a thickness of the barrier layer.

### Claim 5 (depends on 4)

The transistor device of claim 4, further comprising a further barrier layer arranged to line a bottom surface of the recess.

### Claim 6 (depends on 1)

The transistor device of claim 1, further comprising a metal layer arranged over the passivation layer; wherein at least a part of the metal layer overlaps vertically with the recess of the barrier layer.

### Claim 7 (depends on 1)

The transistor device of claim 1, wherein the barrier layer comprises:
a first barrier portion;
a second barrier portion; and
a gap arranged laterally between the first barrier portion and the second barrier portion separating the first barrier portion and the second barren portion;
wherein the gate terminal extends partially into the gap of the barrier layer, such that the first barrier portion is arranged laterally between the source terminal and the gate terminal, and the second barrier portion is arranged laterally between the drain terminal and the gate terminal.

### Claim 8 (depends on 7)

The transistor device of claim 7, wherein a thickness of the first barrier portion is substantially uniform; and wherein the recess is arranged within the second barrier portion.

### Claim 9 (depends on 7)

The transistor device of claim 7, further comprising a gate dielectric layer arranged at least partially under the gate terminal, wherein the gate dielectric layer lines the gap of the barrier layer.

### Claim 10 (depends on 9)

The transistor device of claim 9, wherein the recess of the barrier layer extends laterally from the gate dielectric layer in a direction towards the drain terminal.

### Claim 11 (depends on 9)

The transistor device of claim 9, further comprising a metal layer arranged between the gate dielectric layer and the gate terminal.

### Claim 12 (depends on 11)

The transistor device of claim 11, wherein at least a part of the metal layer overlaps vertically with the recess of the barrier layer.

### Claim 13 (depends on 12)

The transistor device of claim 12, wherein the metal layer further extends into the gap of the barrier layer.

### Claim 14 (depends on 7)

The transistor device of claim 7, wherein the passivation layer comprises a first passivation segment arranged over the first barrier portion, a second passivation segment arranged over the second barrier portion and a further gap arranged laterally between the first passivation segment and the second passivation segment and separating the first passivation segment and the second passivation segment.

### Claim 15 (depends on 14)

The transistor device of claim 14, wherein the first barrier portion protrudes laterally beyond the first passivation segment in a direction towards the gate terminal.

### Claim 16 (depends on 14)

The transistor device of claim 14, wherein the second passivation segment comprises a recess overlapping vertically with the recess of the barrier layer.

### Claim 17 (depends on 14)

The transistor device of claim 14, wherein the second passivation segment comprises a planar surface facing away from the barrier layer and partially overlapping vertically with the recess of the barrier layer.

### Claim 18 (depends on 1)

The transistor device of claim 1, wherein the transistor device is a high electron mobility transistor device.

### Claim 19

A method of forming a transistor device, the method comprising:
providing a substrate;
forming a buffer layer over the substrate;
forming a source terminal, a drain terminal, and a barrier layer directly on the buffer layer, wherein the barrier layer comprises a recess; wherein the barrier layer is disposed laterally between the source terminal and the dram terminal;
forming a passivation layer over the barrier layer, wherein the passivation layer extends into the recess of the barrier layer overlapping vertically and horizontally with the barrier layer;
forming a gate terminal over the buffer layer, wherein the gate terminal is arranged laterally between the source terminal and the drain terminal, wherein a part of the gate terminal is arranged over the passivation layer, and wherein the recess of the barrier layer is arranged laterally between the gate terminal and the drain terminal, and
forming a gate dielectric layer arranged over the passivation layer, the gate dielectric layer overlapping vertically and horizontally with the passivation layer, wherein the gate dielectric layer and the passivation layer are made of different materials.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the barrier layer over the buffer layer and the passivation layer over the barrier layer comprises:
forming a layer of barrier material over the buffer layer;
forming a first trench within the layer of barrier material;
forming a layer of passivation material over the layer of barrier material, wherein the layer of passivation material comprises a second trench narrower than the first trench; and
forming the barrier layer and the passivation layer from the layer of barrier material and the layer of passivation material, respectively.