# US 11,444,163 B2 · Channel structure having tunneling layer with adjusted nitrogen weight percent and methods for forming the same

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- Number: US 11,444,163 B2
- Document ID: US11444163B2
- Status: Granted
- Kind: B2
- Application number: 16/860,971
- Filed: 2020-04-28
- Published: 2021-07-15
- Granted: 2022-09-13
- Earliest claimed: 2020-01-14
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Song Liu; Chao Shen; Dejian Chen; Wenting Wang; Xinxin Huang; Zhiping Xu
- Web page: https://patentgrep.com/patent/US11444163B2

## CPC

- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of memory devices and fabrication methods thereof are disclosed. In an example, a memory device includes a substrate, a memory stack, and a channel structure. The memory stack includes interleaved conductor layers and dielectric layers over the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer that includes a tunneling layer of which a nitrogen weight percent is not greater than about 28%.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a memory stack comprising interleaved conductor layers and dielectric layers over the substrate; and
a channel structure extending through the memory stack into the substrate, wherein the channel structure comprises a functional layer that comprises a tunneling layer, the tunneling layer comprising a plurality of silicon oxynitride layers and a silicon oxide layer such that a nitrogen weight percent of the plurality of silicon oxynitride layers and the silicon oxide layer is not greater than about 28%.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the functional layer further comprises a blocking layer and a memory layer, the blocking layer, the memory layer, and the tunneling layer arranged radially from a sidewall to a center of the channel structure.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the nitrogen weight percent is in a range of about 10% to about 28%.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein an oxygen weight percent in the tunneling layer is in a range of about 32% to about 46%, and the oxygen weight percent is higher than the nitrogen weight percent.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the channel structure further comprises:
a semiconductor layer over the tunneling layer; and
a dielectric core over the semiconductor layer and filling up the channel structure.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the tunneling layer comprises silicon oxynitride.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the tunneling layer comprises a composite structure that comprises a plurality of silicon oxynitride layers.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising a semiconductor plug in contact with the substrate and the channel structure.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the nitrogen weight percent is no greater than about 20%.

### Claim 10

A method for forming a memory device, comprising:
forming a channel hole in a stack structure over a substrate;
depositing, sequentially, a blocking layer and a memory layer radially from a sidewall of the channel hole towards a center of the channel hole;
after the deposition of the blocking layer and the memory layer, depositing a tunneling layer in direct contact with the memory layer;
performing a thermal treatment to adjust a nitrogen weight content in the tunneling layer to be no greater than about 28%; and
depositing a semiconductor layer in direct contact with the tunneling layer in the channel hole after the thermal treatment.

### Claim 11 (depends on 10)

The method of claim 10, wherein the thermal treatment reduces the nitrogen weight content in the tunneling layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein performing the thermal treatment comprises performing an annealing process.

### Claim 13 (depends on 12)

The method of claim 12, wherein performing the annealing process comprises providing an annealing atmosphere filled with oxygen gas.

### Claim 14 (depends on 13)

The method of claim 13, wherein performing the annealing process comprises providing the annealing atmosphere filled with a mixture of oxygen gas and hydrogen chloride gas.

### Claim 15 (depends on 14)

The method of claim 14, wherein a flow rate of oxygen gas is higher than a flow rate of hydrogen chloride gas.

### Claim 16 (depends on 12)

The method of claim 12, wherein providing the annealing process further comprises providing at least one of an annealing time period, an annealing temperature, or an annealing pressure, and wherein
the annealing time period is in a range of about 20 minutes to about 150 minutes;
the annealing temperature is in a range of about 700 degrees Celsius to about 1000 degrees Celsius; and
the annealing pressure is about standard atmospheric pressure.

### Claim 17 (depends on 11)

The method of claim 11, wherein the thermal treatment reduces a number of defects in the tunneling layer.

### Claim 18 (depends on 10)

The method of claim 10, wherein performing the thermal treatment comprises adjusting a parameter value of the thermal treatment in consecutive time periods, the parameter value comprising at least one of a treatment pressure, a treatment temperature, or a flow rate of a gas.

### Claim 19 (depends on 10)

The method of claim 10, wherein depositing the blocking layer, the memory layer, and the tunneling layer each comprise atomic layer deposition (ALD).

### Claim 20 (depends on 10)

The method of claim 10, wherein the semiconductor layer is deposited after thermal treatment without intermediate steps.