# US 11,444,162 B2 · Backside contact with air spacer

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- Number: US 11,444,162 B2
- Document ID: US11444162B2
- Status: Granted
- Kind: B2
- Application number: 17/159,423
- Filed: 2021-01-27
- Published: 2022-07-28
- Granted: 2022-09-13
- Earliest claimed: 2021-01-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Ming Lee; Wei-Yang Lee
- Web page: https://patentgrep.com/patent/US11444162B2

## CPC

- H10D 64/01: Manufacture or treatment
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10P 14/40: of conductive or resistive materials
- H10P 50/266: {by vapour etching only}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10W 20/46: comprising air gaps
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

## Claims

### Claim 1

A method comprising:
performing a first etching process on a backside of a substrate to expose a dummy contact structure;
performing a first deposition process to deposit a first dielectric layer around the dummy contact structure;
performing a second deposition process to deposit an oxide layer on the first dielectric layer;
removing the dummy contact structure to form a trench;
depositing a sacrificial layer on sidewalls of the trench;
depositing a second dielectric layer on the sacrificial layer;
filling the trench with a conductive material; and
removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dielectric layer comprises silicon nitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second dielectric layer comprises silicon nitride.

### Claim 4 (depends on 1)

The method of claim 1, wherein the sacrificial layer comprises silicon.

### Claim 5 (depends on 4)

The method of claim 4, wherein the sacrificial layer is formed using a thermal deposition process.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the dummy contact structure comprises a dry etching process.

### Claim 7 (depends on 1)

The method of claim 1, further comprising, forming a seal on top of the air spacer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the seal comprises a dielectric material.

### Claim 9 (depends on 1)

The method of claim 1, further comprising, before filling the trench implanting a dopant into a source/drain region exposed at a bottom of the trench.

### Claim 10

A method comprising:
applying an etching process to remove a dummy contact structure from a backside of a substrate and expose a source/drain region at a bottom of a trench;
depositing a sacrificial layer on sidewalls of the trench;
depositing a dielectric layer on the sacrificial layer;
filling the trench with a conductive material; and
removing the sacrificial layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising, after depositing the dielectric layer on the sacrificial layer, applying a dry etching process to remove portions of the dielectric layer from the bottom of the trench.

### Claim 12 (depends on 10)

The method of claim 10, further comprising, rounding top corners of the trench before depositing the sacrificial layer.

### Claim 13 (depends on 10)

The method of claim 10, further comprising, before removing the dummy contact structure, removing a silicon material from around the dummy contact structure.

### Claim 14 (depends on 13)

The method of claim 13, further comprising, before removing the dummy contact structure, forming an oxide layer around the dummy contact structure.

### Claim 15 (depends on 10)

The method of claim 10, wherein removing the sacrificial layer leaves an air gap adjacent to the dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising, depositing a seal to close the air gap.

### Claim 17 (depends on 10)

The method of claim 10, wherein the sacrificial layer is formed using a thermal Chemical Vapor Deposition (CVD) process.

### Claim 18

A semiconductor structure comprising:
a substrate having a frontside and a backside;
a transistor formed on the frontside of the substrate, the transistor comprising a source/drain region;
a contact extending from a bottom of the source/drain region to the backside of the substrate, wherein the contact is in direct contact with the source/drain region; and
a first dielectric layer positioned along sides of the contact;
an air gap positioned between the first dielectric layer and a second dielectric layer.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, further comprising, a seal structure formed on a bottom of the air gap, wherein a portion of the seal structure is between the first dielectric layer and the second dielectric layer.

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein the first dielectric layer comprises silicon nitride.