# US 11,444,160 B2 · Integrated circuit (IC) structure with body contact to well with multiple diode junctions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,160 B2 - Document ID: US11444160B2 - Status: Granted - Kind: B2 - Application number: 17/155,182 - Filed: 2021-01-22 - Published: 2022-06-16 - Granted: 2022-09-13 - Earliest claimed: 2020-12-11 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GLOBALFOUNDRIES U.S. Inc. - Inventors: Anupam Dutta; Venkata N. R. Vanukuru; John J. Ellis-Monaghan - Web page: https://patentgrep.com/patent/US11444160B2 ## CPC - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 30/027: {of lateral single-gate IGFETs} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/378: {Contact regions to the substrate regions} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 10/30: Isolation regions comprising PN junctions - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 64/529: {Electrodes for IGFETs contacting substrate regions, e.g. for grounding or preventing parasitic effects} - H10P 30/204: {into Group IV semiconductors} - H10P 30/208: {of electrically inactive species} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well. ## Claims ### Claim 1 An integrated circuit (IC) structure, comprising: a first doped well within a substrate, the first doped well having a first doping type; a transistor structure on the first doped well; a first dopant extension region within the first doped well, the first dopant extension region having the first doping type in a higher concentration than an adjacent portion of the first doped well; a trench isolation (TI) adjacent a portion of the first doped well; and a second doped well within the substrate and coupled to a body contact, the second doped well having a second doping type opposite the first doping type, wherein a sidewall of the TI horizontally abuts the second doped well, a boundary between the second doped well and the first doped well defines a first diode junction, and a boundary between the second doped well and the substrate defines a second diode junction. ### Claim 2 (depends on 1) The IC structure of claim 1, wherein the second doped well includes: a resistive region beneath the body contact to the second doped well, and having a sidewall horizontally adjacent the TI; and a conductive region beneath the resistive region. ### Claim 3 (depends on 1) The IC structure of claim 1, wherein the adjacent portion of the first doped well is vertically between a bottom surface of the TI and an underlying portion of the second doped well. ### Claim 4 (depends on 1) The IC structure of claim 1, wherein the TI horizontally surrounds the first doped well, and a portion of the second doped well horizontally surrounds the TI. ### Claim 5 (depends on 1) The IC structure of claim 1, wherein the transistor structure includes a set of source/drain regions within the first doped well, and wherein a depth of the set of source/drain regions within the first doped well is at most approximately one-tenth of a depth of the first doped well from a top surface of the substrate. ### Claim 6 (depends on 1) The IC structure of claim 1, wherein the dopant extension region is adjacent the first diode junction, the boundary between the second doped well and the first doped well is a first vertical boundary, and the boundary between the second doped well and the substrate is a second vertical boundary. ### Claim 7 (depends on 1) The IC structure of claim 1, wherein the second doped well includes a second dopant extension region adjacent the first diode junction, the second dopant extension region having the second doping type in a different concentration than an adjacent portion of the second doped well. ### Claim 8 An integrated circuit (IC) structure, comprising: a first doped well within a substrate, the first doped well having a first doping type; a transistor structure on the first doped well; a first dopant extension region within the first doped well, the first dopant extension region having the first doping type in a higher concentration than an adjacent portion of the first doped well; a trench isolation (TI) adjacent a portion of the first doped well; a second doped well within the substrate, the second doped well having a second doping type opposite the first doping type, wherein the second doped well includes: a first portion beneath the first doped well, wherein a boundary between the first portion of the second doped well and the first doped well defines a first diode junction, and a boundary between the first portion of the second doped well and the substrate defines a second diode junction, and a second portion coupled to a body contact and having a bottom surface substantially coplanar with a bottom surface of the first portion, wherein the second portion includes a sidewall adjacent the first portion of the second doped well and adjacent the TI. ### Claim 9 (depends on 8) The IC structure of claim 8, wherein the second portion of the second doped well includes: a resistive region beneath the body contact to the second doped well; and a conductive region beneath the resistive region. ### Claim 10 (depends on 8) The IC structure of claim 8, wherein the adjacent portion of the first doped well is vertically between a bottom surface of the TI and the first portion of the second doped well. ### Claim 11 (depends on 8) The IC structure of claim 8, wherein the TI horizontally surrounds the first doped well, and the second portion of the second doped well horizontally surrounds the TI. ### Claim 12 (depends on 8) The IC structure of claim 8, wherein the transistor structure includes a set of source/drain regions within the first doped well, and wherein a depth of the set of source/drain regions within the first doped well is at most approximately one-tenth of a depth of the first doped well from a top surface of the substrate. ### Claim 13 (depends on 8) The IC structure of claim 8, wherein the first dopant extension region is adjacent the first diode junction, the boundary between the second doped well and the first doped well is a first vertical boundary, and the boundary between the second doped well and the substrate is a second vertical boundary. ### Claim 14 (depends on 8) The IC structure of claim 8, wherein the second doped well includes a second dopant extension region adjacent the first diode junction, the second dopant extension region having the second doping type in a different concentration than an adjacent portion of the second doped well. ### Claim 15 A method of forming an integrated circuit (IC) structure, the method comprising: forming a first doped well of a first doping type within a substrate forming a first dopant extension region within the first doped well, the first dopant extension region having the first doping type in a higher concentration than an adjacent portion of the first doped well; forming a trench isolation (TI) adjacent a sidewall of the first doped well; forming a second doped well of a second doping type within the substrate, wherein a vertical boundary between the first portion of the second doped well and the first doped well defines a first diode junction, and a vertical boundary between the first portion of the second doped well and the substrate defines a second diode junction; forming a transistor structure on the first doped well; and forming a body contact to a second portion of the second doped well. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming a resistive region within the second doped well, wherein forming the body contact causes the body contact to be coupled to the resistive region within the second doped well. ### Claim 17 (depends on 15) The method of claim 15, wherein forming the TI includes forming the TI circumferentially about the first doped well. ### Claim 18 (depends on 15) The method of claim 15, wherein forming the transistor structure includes forming a set of source/drain regions within the first doped well to a depth of at most approximately one-tenth of a depth of the first doped well from a top surface of the substrate. ### Claim 19 (depends on 15) The method of claim 15, further comprising forming a second dopant extension region within the second doped well, the second dopant extension region having the second doping type in a higher concentration than an adjacent portion of the second doped well.