# US 11,444,159 B2 · Field effect transistors with wide bandgap materials

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,159 B2
- Document ID: US11444159B2
- Status: Granted
- Kind: B2
- Application number: 16/612,259
- Filed: 2017-06-30
- Published: 2020-02-27
- Granted: 2022-09-13
- Earliest claimed: 2017-06-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Sean T. Ma; Gilbert Dewey; Willy Rachmady; Matthew V. Metz; Cheng-Ying Huang; Harold W. Kennel; Jack T. Kavalieros; Anand S. Murthy; Tahir Ghani
- Web page: https://patentgrep.com/patent/US11444159B2

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

## Claims

### Claim 1

An electronic device comprising:
a semiconductor channel layer on a semiconductor buffer layer on a substrate, wherein the semiconductor buffer layer and a portion of the semiconductor channel layer are in a trench in a dielectric layer above the substrate, the semiconductor channel layer having a first portion and a second portion laterally adjacent to the first portion, the first portion comprising a first semiconductor, the second portion comprising a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor; and
a gate electrode on the semiconductor channel layer, wherein the first portion of the semiconductor channel layer comprises an undercut region extending laterally underneath the gate electrode, and wherein the second portion is in the undercut region.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium phosphide antimonide (InxGa1-xPySb1-y), indium aluminum arsenide antimonide (InxAl1-xAsySb1-y), indium aluminum arsenide phosphide (InxAl1-xAsySb1-y), where 0.ltoreq.x.ltoreq.1, 0≤y≤1, or any combination thereof.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the second semiconductor comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAsxSb1-x) (where 0≤x≤1), indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium arsenide phosphide antimonide InxGa1-xPySb1-y (where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide InxAl1-xAsySb1-y, indium aluminum arsenide phosphide (InxAl1-xAsyP1-y) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the width of the second portion is from 5 nanometers to 10 nanometers.

### Claim 8 (depends on 1)

The electronic device of claim 1, further comprising a source/drain region in a recess in the semiconductor channel layer; and a gate dielectric on the semiconductor channel layer.

### Claim 9

A system comprising:
a chip including an electronic device comprising a semiconductor channel layer on a semiconductor buffer layer on a substrate, wherein the semiconductor buffer layer and a portion of the semiconductor channel layer are in a trench in a dielectric layer above the substrate, the semiconductor channel layer having a first portion and a second portion laterally adjacent to the first portion, the first portion comprising a first semiconductor, the second portion comprising a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor; and
a gate electrode on the semiconductor channel layer, wherein the first portion of the semiconductor channel layer comprises an undercut region extending laterally underneath the gate electrode, and wherein the second portion is in the undercut region.

### Claim 10 (depends on 9)

The system of claim 9, wherein the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

### Claim 11 (depends on 9)

The system of claim 9, wherein the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

### Claim 12 (depends on 9)

The system of claim 9, wherein each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

### Claim 13 (depends on 9)

The system of claim 9, wherein the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium phosphide antimonide (InxGa1-xPySb1-y) indium aluminum arsenide antimonide (InxAl1-xAsySb1-y), indium aluminum arsenide phosphide (InxAl1-xAsyP1-y), where 0≤x≤1, 0≤y≤1, or any combination thereof.

### Claim 14 (depends on 9)

The system of claim 9, wherein the second semiconductor comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAsxSb1-x) (where 0≤x≤1), indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium arsenide phosphide antimonide InxGa1-xPySb1-y(where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide InxAl1-xAsySb1-y, indium aluminum arsenide phosphide (InxAl1-xAsyP1-y) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.

### Claim 15 (depends on 9)

The system of claim 9, wherein the width of the second portion is from 5 nanometers to 10 nanometers.

### Claim 16 (depends on 9)

The system of claim 9, further comprising a source/drain region on the semiconductor buffer layer; and a gate dielectric on the semiconductor channel layer.

### Claim 17

A method to manufacture an electronic device, comprising:
depositing a semiconductor channel layer comprising a first semiconductor on a semiconductor buffer layer on a substrate, wherein the semiconductor buffer layer and a portion of the semiconductor channel layer formed in a trench in a dielectric layer above the substrate;
forming a gate electrode on the semiconductor channel layer;
forming an undercut region in the semiconductor channel layer to form an undercut Portion of the semiconductor channel layer;
depositing a second semiconductor in the undercut region, wherein the second semiconductor that has a bandgap greater than a bandgap of the first semiconductor, and wherein the second semiconductor is laterally adjacent to the undercut portion of the semiconductor channel layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second semiconductor has a conduction band that has a zero offset relative to the conduction band of the first semiconductor.

### Claim 19 (depends on 17)

The method of claim 17, wherein the second semiconductor has a dopant concentration equal or smaller than 10{circumflex over ( )}16 atoms/cm{circumflex over ( )}3.

### Claim 20 (depends on 17)

The method of claim 17, wherein each of the first semiconductor and the second semiconductor comprises a III-V semiconductor material.

### Claim 21 (depends on 17)

The method of claim 17, wherein the first semiconductor comprises indium gallium arsenide, indium arsenide, indium antimonide, indium gallium antimonide, indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium phosphide antimonide (InxGa1-xPySb1-y), indium aluminum arsenide antimonide (InxAl1-xAsySb1-y), indium aluminum arsenide phosphide (InxAl1-xAsyP1-y), where 0≤x≤1, 0≤y≤1, or any combination thereof.

### Claim 22 (depends on 17)

The method of claim 17, wherein the second semiconductor comprises gallium arsenide, indium phosphide, gallium phosphide, indium gallium phosphide, aluminum gallium arsenide, gallium arsenide antimonide (GaAsxSb1-x) (where 0≤x≤1), indium gallium arsenide antimonide (InxGa1-xAsySb1-y), indium gallium arsenide phosphide (InxGa1-xAsyP1-y), indium gallium arsenide phosphide antimonide InxGa1-xPySb1-y(where 0≤x≤0.3, 0≤y≤1), indium aluminum arsenide antimonide InxAl1-xAsySb1-y, indium aluminum arsenide phosphide (InxAl1-xAsyP1-y) (where 0.8≤x≤1, 0≤y≤1), or any combination thereof.

### Claim 23 (depends on 17)

The method of claim 17, wherein the width of the second portion is from 5 nanometers to 10 nanometers.

### Claim 24 (depends on 17)

The method of claim 17, further comprising:
forming a spacer on the gate electrode; etching a portion of the semiconductor channel layer outside the gate electrode to form a recess; and
depositing a source/drain region in the recess.