# US 11,444,156 B2 · Semiconductor device

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- Number: US 11,444,156 B2
- Document ID: US11444156B2
- Status: Granted
- Kind: B2
- Application number: 16/858,274
- Filed: 2020-04-24
- Published: 2021-02-04
- Granted: 2022-09-13
- Earliest claimed: 2019-08-01
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Hayato Okamoto; Ze Chen
- Web page: https://patentgrep.com/patent/US11444156B2

## CPC

- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/114: {PN junction isolations}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/128: {Anode regions of diodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view. The electrode does not have contact with the fourth and fifth semiconductor regions but has contact with the third semiconductor region.

## Claims

### Claim 1

A semiconductor device, comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type located on the first semiconductor region;
a third semiconductor region of the second conductivity type located on the second semiconductor region and having a higher impurity concentration than the second semiconductor region;
a fourth semiconductor region of the second conductivity type having a higher impurity concentration than the second semiconductor region, located separately from the third semiconductor region in a planar view, and having contact with the second semiconductor region;
a fifth semiconductor region of the first conductivity type located on the second semiconductor region and located between the third and fourth semiconductor regions in a planar view, wherein the third semiconductor region is in direct contact with the fifth semiconductor region; and
an electrode not in direct contact with the fourth and fifth semiconductor regions but having contact with the third semiconductor region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
a depth of the fifth semiconductor region is equal to or larger than a depth of the third semiconductor region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the electrode is in direct contact with the third semiconductor region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
a portion of the fourth semiconductor region sandwiches a part of the second semiconductor region in a direction perpendicular to a depth direction of the second semiconductor region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
a depth of a bottom surface of the fourth semiconductor region is greater than a depth of a bottom surface of the third semiconductor region and is greater than a depth of a bottom surface of the fifth semiconductor region.