# US 11,444,155 B2 · Silicon carbide semiconductor device

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- Number: US 11,444,155 B2
- Document ID: US11444155B2
- Status: Granted
- Kind: B2
- Application number: 17/316,178
- Filed: 2021-05-10
- Published: 2021-08-26
- Granted: 2022-09-13
- Earliest claimed: 2018-06-22
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Andreas Huerner; Dethard Peters
- Web page: https://patentgrep.com/patent/US11444155B2

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 84/035: {using silicon carbide [SiC] technology}
- H10D 30/615: {comprising a MOS gate electrode and at least one non-MOS gate electrode}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/82: of only field-effect components
- H10D 62/405: {Orientations of crystalline planes}
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.

## Claims

### Claim 1

A silicon carbide semiconductor device, comprising:
a first load electrode disposed on a first surface of a silicon carbide semiconductor body;
a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode; and
an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor comprising a source region and a body region, the body region being electrically connected to the first load electrode,
wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.

### Claim 2 (depends on 1)

The silicon carbide device of claim 1, further comprising a second doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, wherein the source and body regions are disposed between a gate structure of the insulated gate field effect transistor and the second doped region, wherein the second doped region forms a p-n junction with the first doped region, and wherein a depletion region extending from the p-n junction increases the resistance of the first doped region as the load current in the insulated gate field effect transistor rises.

### Claim 3 (depends on 2)

The silicon carbide device of claim 2, wherein the geometry and dopant concentration of the first doped region is such that the first doped region is fully pinched off by the depletion region at sufficient load current in the insulated gate field effect transistor.

### Claim 4 (depends on 2)

The silicon carbide device of claim 2, wherein the depletion region expands away from the p-n junction between the first and second doped regions and away from a second p-n junction between the source region and the body region as the load current in the insulated gate field effect transistor rises.

### Claim 5 (depends on 2)

The silicon carbide device of claim 2, wherein the silicon carbide semiconductor device comprises a continuous doped region of a single conductivity type, and wherein the first doped region and the source region are parts of the continuous doped region.

### Claim 6 (depends on 5)

The silicon carbide device of claim 5, wherein a first end of the continuous doped region contacts the first load electrode at the first surface, and wherein a second end of the continuous doped region contacts the gate structure of the insulated gate field effect transistor.

### Claim 7 (depends on 5)

The silicon carbide device of claim 5, wherein any one or more of the following is arranged at the first surface between the first doped region and the gate structure: an electrically insulating region, an electrically conductive region, a semiconductor region of opposite conductivity type as the source region, a semiconductor region of the same conductivity type and lower dopant concentration as the first doped region.

### Claim 8 (depends on 1)

The silicon carbide device of claim 1, further comprising a contact portion that electrically connects the first doped region to the first load electrode, wherein a maximum dopant concentration in the first doped region is at most 10% of a maximum dopant concentration in the contact portion.

### Claim 9 (depends on 1)

The silicon carbide semiconductor device of claim 1, wherein the insulated gate field effect transistor comprises a trench gate structure.

### Claim 10 (depends on 1)

The silicon carbide semiconductor device of claim 1, further comprising a plurality of transistor cells, wherein each transistor cell of the plurality of transistor cells comprises one of the insulated gate field effect transistors and one of the first doped regions.

### Claim 11

A silicon carbide semiconductor device, comprising:
a first load electrode disposed on a first surface of a silicon carbide semiconductor body;
a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode;
an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor comprising a source region and a body region, the body region being electrically connected to the first load electrode;
a second doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode,
wherein the second doped region forms a p-n junction with the first doped region, and wherein a depletion region extending from the p-n junction increases a resistance of the first doped region by at least a factor of two as load current in the insulated gate field effect transistor rises.

### Claim 12 (depends on 11)

The silicon carbide device of claim 11, wherein a geometry and dopant concentration of the first doped region is such that the first doped region is fully pinched off by the depletion region at sufficient load current in the insulated gate field effect transistor.