# US 11,444,153 B2 · Method of forming stress memorization layer on backside of semiconductor substrate and semiconductor device thereof

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- Number: US 11,444,153 B2
- Document ID: US11444153B2
- Status: Granted
- Kind: B2
- Application number: 16/542,667
- Filed: 2019-08-16
- Published: 2021-02-18
- Granted: 2022-09-13
- Earliest claimed: 2019-08-16
- Assignees: Applied Materials, Inc.
- Applicants: APPLIED Materials, Inc.
- Inventors: Qintao Zhang; Wei Zou
- Web page: https://patentgrep.com/patent/US11444153B2

## CPC

- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.

## Claims

### Claim 1

A method, comprising:
providing a substrate having a first main side opposite a second main side;
depositing a stack of layers atop the first main side of the substrate;
implanting the second main side of the substrate to form an amorphous implant area;
forming a stress liner over the second main side of the substrate; and
annealing the stress liner to form a stress memorization layer in the amorphous implant area.

### Claim 2 (depends on 1)

The method of claim 1, further comprising removing the stress liner after the stress memorization layer is formed.

### Claim 3 (depends on 1)

The method of claim 1, wherein the stack of layers is formed atop the first main side of the substrate before the second main side of the substrate is implanted.

### Claim 4 (depends on 1)

The method of claim 1, wherein the stress memorization layer is formed along just a portion of the second main side of the substrate.

### Claim 5 (depends on 1)

The method of claim 1, wherein the stress memorization layer is formed by a solid-phase epitaxy regrowth process.

### Claim 6 (depends on 1)

The method of claim 1, wherein implanting the second main side of the substrate to form the amorphous implant area comprises implanting the second main side with germanium, silicon, or tin.

### Claim 7 (depends on 1)

The method of claim 1, further comprising etching the stress liner to remove the stress liner over the stress memorization layer.

### Claim 8

A method for forming a semiconductor device, comprising:
depositing a stack of layers atop a first main side of a substrate;
implanting a second main side of the substrate to form an amorphous implant area;
forming a stress liner along the second main side of the substrate;
annealing the stress liner to form a stress memorization layer in the amorphous implant area along the second main side of the substrate; and
removing the stress liner from along the stress memorization layer and from along the second main side of the substrate.

### Claim 9 (depends on 8)

The method of claim 8, wherein the stack of layers is formed atop the first main side of the substrate before the second main side of the substrate is implanted.

### Claim 10 (depends on 8)

The method of claim 8, wherein the stack of layers is formed atop the first main side of the substrate after the second main side of the substrate is implanted.

### Claim 11 (depends on 8)

The method of claim 8, wherein the stress memorization layer is formed along just a portion of the second main side of the substrate.

### Claim 12 (depends on 8)

The method of claim 8, wherein just a portion of the second main side of the substrate is implanted to form the amorphous implant area.

### Claim 13 (depends on 8)

The method of claim 8, wherein the stress memorization layer is formed by a solid-phase epitaxy regrowth process.

### Claim 14 (depends on 8)

The method of claim 8, wherein implanting the second main side of the substrate to form the amorphous implant area comprises implanting the second main side with germanium, silicon, or tin.

### Claim 15 (depends on 8)

The method of claim 8, further comprising etching the stress liner to remove the stress liner from over the stress memorization layer.

### Claim 16

A semiconductor device, comprising:
a stack of layers formed atop a first main side of a substrate; and
a stress memorization layer formed in a second main side of the substrate, wherein the second main side of the substrate is a backside of the substrate.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the stress memorization layer is formed along just a portion of the second main side of the substrate.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the stress memorization layer is a solid-phase epitaxial layer.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the stress memorization layer includes germanium, silicon, or tin.