# US 11,444,152 B2 · Inversion channel devices on multiple crystal orientations

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- Number: US 11,444,152 B2
- Document ID: US11444152B2
- Status: Granted
- Kind: B2
- Application number: 17/007,014
- Filed: 2020-08-31
- Published: 2022-03-03
- Granted: 2022-09-13
- Earliest claimed: 2020-08-31
- Assignees: GeneSiC Semiconductor Inc.
- Applicants: GeneSiC Semiconductor Inc.
- Inventors: Siddarth Sundaresan; Ranbir Singh; Jaehoon Park
- Web page: https://patentgrep.com/patent/US11444152B2

## CPC

- H10D 62/405: {Orientations of crystalline planes}
- H10D 12/031: {of IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/664: {Inverted VDMOS transistors, i.e. source-down VDMOS transistors}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/8325: {Silicon carbide}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.

## Claims

### Claim 1

A metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a unit cell, the unit cell comprising:
a drift region of a first conductivity type;
a first source region of the first conductivity type and a second source region of the first conductivity type;
a first well region of a second conductivity type and a second well region of the second conductivity type; and
a trench region that extends through the first source region and the first well region,
wherein the second source region is confined within the second well region,
wherein the second well region overlaps a portion of the first well region to form a composite well region at a first section of the unit cell, and
wherein the composite well region is interspersed between the trench region and the drift region at the first section.

### Claim 2 (depends on 1)

The MOSFET device of claim 1, wherein a depth of the trench region ranging from 0.2 μm to 2.0 μm.

### Claim 3 (depends on 1)

The MOSFET device of claim 1, wherein the trench region comprising a trench sidewall comprises a sidewall angle ranging from 30° to 90°.

### Claim 4 (depends on 3)

The MOSFET device of claim 3, wherein the trench sidewall comprises a sloped sidewall.