# US 11,444,151 B2 · Poly-insulator-poly capacitor and fabrication method thereof

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- Number: US 11,444,151 B2
- Document ID: US11444151B2
- Status: Granted
- Kind: B2
- Application number: 17/142,268
- Filed: 2021-01-06
- Published: 2022-06-09
- Granted: 2022-09-13
- Earliest claimed: 2020-12-08
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Linggang Fang
- Web page: https://patentgrep.com/patent/US11444151B2

## CPC

- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

## Claims

### Claim 1

A poly-insulator-poly (PIP) capacitor, comprising:
a semiconductor substrate comprising a capacitor forming region;
a first capacitor dielectric layer disposed on the capacitor forming region;
a first poly electrode disposed on the first capacitor dielectric layer;
a second capacitor dielectric layer disposed on the first poly electrode;
a second poly electrode disposed on the second capacitor dielectric layer, wherein the first poly electrode comprises a contact portion that protrudes beyond an end surface of the second poly electrode;
a third poly electrode disposed adjacent to a first sidewall of the second poly electrode;
a third capacitor dielectric layer disposed between the third poly electrode and the second poly electrode;
a fourth poly electrode disposed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall;
a hard mask layer capping the second poly electrode, and wherein a top surface of the hard mask layer is flush with a top surface of the fourth poly electrode; and
a fourth capacitor dielectric layer disposed between the fourth poly electrode and the second poly electrode, wherein the first poly electrode, the third poly electrode, and the fourth poly electrode are electrically connected to an anode.

### Claim 2 (depends on 1)

The PIP capacitor according to claim 1, wherein the second poly electrode is electrically connected to a cathode, and wherein the third poly electrode, the third capacitor dielectric layer, and the second poly electrode constitute a first capacitor, the first poly electrode, the second capacitor dielectric layer, and the second poly electrode constitute a second capacitor, and the second poly electrode, the fourth capacitor dielectric layer, and the fourth poly electrode constitute a third capacitor.

### Claim 3 (depends on 2)

The PIP capacitor according to claim 2, wherein an ion well is disposed within the capacitor forming region and is electrically connected to the cathode, and wherein the third poly electrode, the first capacitor dielectric layer and the ion well constitute a fourth capacitor, and the first poly electrode, the first capacitor dielectric layer and the ion well constitute a fifth capacitor.

### Claim 4 (depends on 3)

The PIP capacitor according to claim 3, wherein a fifth capacitor dielectric layer is disposed between the fourth poly electrode and the semiconductor substrate, wherein the fifth capacitor dielectric layer is thicker than the first capacitor dielectric layer, and wherein the fourth poly electrode, the fifth capacitor dielectric layer, and the ion well constitute a sixth capacitor.

### Claim 5 (depends on 1)

The PIP capacitor according to claim 1, wherein a width of the first poly electrode is greater than a width of the second poly electrode.

### Claim 6 (depends on 1)

The PIP capacitor according to claim 1, wherein the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer comprise an oxide-nitride-oxide (ONO) dielectric layer.

### Claim 7 (depends on 1)

The PIP capacitor according to claim 1, wherein the third capacitor dielectric layer and the fourth capacitor dielectric layer are in direct contact with a top surface of the first poly electrode.

### Claim 8 (depends on 1)

The PIP capacitor according to claim 1, wherein the capacitor forming region is a trench isolation region.