# US 11,444,127 B2 · Memory devices

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- Number: US 11,444,127 B2
- Document ID: US11444127B2
- Status: Granted
- Kind: B2
- Application number: 17/019,649
- Filed: 2020-09-14
- Published: 2021-10-07
- Granted: 2022-09-13
- Earliest claimed: 2020-04-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jinwoo Lee; Kwangmin Park; Zhe Wu
- Web page: https://patentgrep.com/patent/US11444127B2

## CPC

- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

## Claims

### Claim 1

A memory device, comprising:
a first conductive line on a substrate and extending in a first horizontal direction;
a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and
a memory cell between the first conductive line and the second conductive line, the memory cell:
including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern,
extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and
having a tapered shape with a decreasing horizontal width along the vertical direction,
wherein:
at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level,
the variable resistance memory layer includes a recess in side walls thereof, and
the buffer resistance layer fills the recess.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1, wherein:
the variable resistance memory layer has a circular horizontal cross-section, and
the buffer resistance layer has a ring-shaped horizontal cross-section surrounding a periphery of the variable resistance memory layer.

### Claim 3 (depends on 1)

The memory device as claimed in claim 1, wherein:
the variable resistance memory layer has a square horizontal cross-section, and
the buffer resistance layer extends along each of lateral sides of the variable resistance memory layer.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1, wherein the recess of the variable resistance memory layer surrounds the variable resistance memory layer along the side walls of the variable resistance memory layer.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1, wherein the recess of the variable resistance memory layer extends in the first horizontal direction along each of the side walls of the variable resistance memory layer.

### Claim 6 (depends on 1)

The memory device as claimed in claim 1, wherein:
the memory cell further includes an upper electrode between the second conductive line and the variable resistance memory layer and buffer resistance layer.

### Claim 7 (depends on 1)

The memory device as claimed in claim 1, wherein:
the buffer resistance layer has a circular horizontal cross-section, and
the variable resistance memory layer has a ring-shaped horizontal cross-section surrounding a periphery of the buffer resistance layer.

### Claim 8 (depends on 1)

The memory device as claimed in claim 1, wherein:
the buffer resistance layer has a square horizontal cross-section, and
the variable resistance memory layers have a bar-shaped horizontal cross-sections extending along both lateral sides of the buffer resistance layer.

### Claim 9 (depends on 1)

The memory device as claimed in claim 1, wherein the memory cell has a tapered shape extending from a lower portion to an upper portion in the vertical direction and having a decreasing horizontal width.

### Claim 10

A memory device, comprising:
a plurality of first conductive lines on a substrate and extending in a first horizontal direction;
a plurality of second conductive lines on the plurality of first conductive lines and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and
a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines, each memory cell of the plurality of memory cells including: a lower electrode, an intermediate electrode, an upper electrode, a variable resistance memory layer and a buffer resistance layer, which are connected between the intermediate electrode and the upper electrode in parallel, and a switch material pattern between the lower electrode and the intermediate electrode,
wherein:
the variable resistance memory layer includes a recess that is concave,
the recess in the variable resistance memory layer is in side walls thereof, and
the buffer resistance layer has an inner side wall that is convex to fill the recess.

### Claim 11 (depends on 10)

The memory device as claimed in claim 10, wherein the buffer resistance layer surrounds a periphery of the variable resistance memory layer.

### Claim 12 (depends on 10)

The memory device as claimed in claim 10, wherein, in each of the plurality of memory cells, buffer resistance layers extend along both lateral sides of the variable resistance memory layer.

### Claim 13 (depends on 10)

The memory device as claimed in claim 10, wherein the variable resistance memory layer surrounds a periphery of the buffer resistance layer.

### Claim 14 (depends on 10)

The memory device as claimed in claim 10, wherein, in each of the plurality of memory cells, variable resistance memory layers extend along both lateral sides of the buffer resistance layer.

### Claim 15

A memory device, comprising:
a plurality of first conductive lines on a substrate and extending in a first horizontal direction;
a plurality of second conductive lines on the plurality of first conductive lines and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and
a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines, each memory cell of the plurality of memory cells including: a lower electrode, an intermediate electrode, an upper electrode, a variable resistance memory layer and a buffer resistance layer, which are connected between the intermediate electrode and the upper electrode in parallel, and a switch material pattern between the lower electrode and the intermediate electrode,
wherein:
the variable resistance memory layer has a circular horizontal cross-section, and
the buffer resistance layer has a ring-shaped horizontal cross-section surrounding a periphery of the variable resistance memory layer, the buffer resistance layer including a material having a resistivity that is less than a resistivity of the variable resistance memory layer in a high-resistance state and greater than a resistivity of the variable resistance memory layer in a low-resistance state.

### Claim 16 (depends on 15)

The memory device as claimed in claim 15, wherein the variable resistance memory layer includes a recess that is concave and surrounds the variable resistance memory layer along side walls of the variable resistance memory layer.

### Claim 17 (depends on 16)

The memory device as claimed in claim 16, wherein the buffer resistance layer includes an inner side wall that is convex to fill the recess.

### Claim 18 (depends on 15)

The memory device as claimed in claim 15, wherein each of the plurality of memory cells has a tapered shape with a decreasing horizontal width along a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction.