# US 11,444,125 B2 · Memory devices and methods of forming memory devices

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- Number: US 11,444,125 B2
- Document ID: US11444125B2
- Status: Granted
- Kind: B2
- Application number: 16/903,503
- Filed: 2020-06-17
- Published: 2021-12-23
- Granted: 2022-09-13
- Earliest claimed: 2020-06-17
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Desmond Jia Jun Loy; Eng Huat Toh; Shyue Seng Tan
- Web page: https://patentgrep.com/patent/US11444125B2

## CPC

- H10B 63/82: {the switching components having a common active material layer}
- G11C 11/5614: {using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/841: {Electrodes}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C 2013/009: {Write using potential difference applied between cell electrodes}
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

## Claims

### Claim 1

A memory device comprising:
a first electrode;
a first mask element arranged over a portion of and laterally offset from the first electrode;
a second electrode arranged over the first mask element;
a second mask element arranged over the second electrode;
a third electrode arranged over a portion of and laterally offset from the second mask element; and
a switching layer arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the switching layer comprises:
a first part between the first electrode and the second electrode; and
a second part between the second electrode and the third electrode;
wherein the first part and the second part comprise a same material.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the second electrode adjoins the first mask element and the second mask element adjoins the second electrode.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the second electrode comprises an inert electrode.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the first electrode and the third electrode comprise different materials.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first electrode and the third electrode comprise a same material.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein a thickness of the second mask element is greater than a thickness of the first mask element.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein a thickness of the first mask element is greater than a thickness of the second mask element.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein a thickness of the first mask element is approximately equal to a thickness of the second mask element.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a first memory cell comprising the first electrode and the second electrode, and a second memory cell comprising the third electrode and the second electrode.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the first memory cell is an oxide-based memory cell and the second memory cell is a conductive-bridge memory cell.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the first memory cell is a conductive-bridge memory cell and the second memory cell is an oxide-based memory cell.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the first memory cell and the second memory cell are a same type of memory cell comprising one of a conductive-bridge memory cell and an oxide-based memory cell.

### Claim 14 (depends on 10)

The memory device of claim 10, wherein the second electrode comprises:
a first electrode layer; and
a second electrode layer arranged over the first electrode layer;
wherein the first memory cell comprises the first electrode and the first electrode layer of the second electrode, and the second memory cell comprises the third electrode and the second electrode layer of the second electrode; and
wherein the first electrode layer and the second electrode layer comprise different materials.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the first electrode layer comprises an oxygen scavenging electrode of the first memory cell and the second electrode layer comprises an active electrode of the second memory cell.

### Claim 16 (depends on 1)

The memory device of claim 1, further comprising a further switching layer arranged along a second side surface of the first mask element, a second side surface of the second electrode and a second side surface of the second mask element.

### Claim 17 (depends on 16)

The memory device of claim 16, further comprising:
a fourth electrode, wherein the first mask element is arranged over a portion of and laterally offset from the fourth electrode; and
a fifth electrode arranged over a portion of and laterally offset from the second mask element;
wherein the further switching layer is arranged between the fourth electrode and the fifth electrode.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the second side surfaces of the first mask element, the second electrode and the second mask element face an opposite direction from the first side surfaces of the first mask element, the second electrode and the second mask element, respectively.

### Claim 19

A method of fabricating a memory device, the method comprising:
forming a first electrode;
forming a first mask element over a portion of the first electrode, wherein the first mask element is laterally offset from the first electrode;
forming a second electrode over the first mask element;
forming a second mask element over the second electrode;
forming a third electrode over a portion of the second mask element, wherein the third electrode is laterally offset from the second mask element; and
forming a switching layer between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the switching layer comprises:
depositing switching material over the second mask element; and
removing a portion of the switching material above the second mask element.