# US 11,444,124 B2 · Hybrid memristor/field-effect transistor memory cell and its information encoding scheme > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,124 B2 - Document ID: US11444124B2 - Status: Granted - Kind: B2 - Application number: 16/630,195 - Filed: 2018-07-11 - Published: 2020-05-21 - Granted: 2022-09-13 - Earliest claimed: 2017-07-26 - Assignees: The Hong Kong University of Science and Technology - Applicants: The Hong Kong University of Science and Technology - Inventors: Kwang Ting Cheng; Miguel Angel Lastras Montaño - Web page: https://patentgrep.com/patent/US11444124B2 ## CPC - G11C 13/003: {Cell access} - H10B 63/82: {the switching components having a common active material layer} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - G11C 2013/0073: {Write using bi-directional cell biasing} - G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver - G11C 2213/79: Array wherein the access device being a transistor - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left-resistive switching device at an internal node, and (c) a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node. ## Claims ### Claim 1 A resistive random-access memory (ReRAM) comprising a hybrid memory cell, wherein the hybrid memory cell comprises: a left resistance-switching device comprising a first terminal and a second terminal, a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left resistance-switching device at an internal node, wherein the second terminal of the left resistance-switching device is directly connected to a word line and the second terminal of the right resistance-switching device is directly connected to a bit line; and a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node. ### Claim 2 (depends on 1) The ReRAM according to claim 1, wherein the left resistance-switching device and the right resistance-switching device are memristors. ### Claim 3 (depends on 1) The ReRAM according to claim 1, wherein the left resistance-switching device and the right resistance-switching device are in opposite resistance states, wherein resistance states include a high resistance state and alow resistance state. ### Claim 4 (depends on 1) The ReRAM according to claim 1, wherein the transistor is a minimum sized transistor. ### Claim 5 (depends on 1) The ReRAM according to claim 1, wherein a logic level of the hybrid memory cell is based on a ratio of resistances of the right resistance-switching device and the left resistance-switching device. ### Claim 6 (depends on 1) The ReRAM according to claim 1, further comprising: peripheral circuitry coupled to the hybrid memory cell, the peripheral circuitry configured to program and/or determine a logic level of the hybrid memory cell. ### Claim 7 (depends on 6) The ReRAM according to claim 6, wherein the peripheral circuitry is configured to determine the logic level by: applying a read voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device; applying a voltage bias at the gate terminal of the transistor; and sensing voltage at the internal node via the source of the transistor. ### Claim 8 (depends on 6) The ReRAM according to claim 6, wherein the peripheral circuitry is configured to program the logic level by: applying a write voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device. ### Claim 9 (depends on 6) The ReRAM according to claim 6, wherein the peripheral circuitry is configured to program the logic level by: applying a write voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device; and applying a voltage bias at the gate of the transistor. ### Claim 10 (depends on 6) The ReRAM according to claim 6, wherein the peripheral circuitry comprises: a word line driver coupled to the second terminal of the left resistance-switching device via the word line; an enable line driver coupled to the gate terminal of the transistor; a bit line driver coupled to the second terminal of the right resistance-switching device via the bit line; and a sense line driver coupled to the source terminal of the transistor. ### Claim 11 (depends on 10) The ReRAM according to claim 10, wherein: the word line driver is configured to provide a first bias to the hybrid memory cell; the enable line driver is configured to select the hybrid memory cell to program and/or determine the logic level; and the bit line driver is configured to provide a second bias to the hybrid memory cell. ### Claim 12 (depends on 1) The ReRAM according to claim 1, wherein the transistor is a p-type transistor or an n-type transistor. ### Claim 13 A method for programming a hybrid memory cell of a resistive random-access memory (ReRAM), the method comprising: applying a write voltage between a second terminal of a left resistance-switching device and a second terminal of a right resistance-switching device, wherein a first terminal of the left resistance-switching device is connected to a first terminal of the right resistance-switching device at an internal node; and removing the write voltage after a predetermined time; wherein the hybrid memory cell comprises the left resistance-switching device, the right resistance-switching device, and a transistor, wherein the second terminal of the left resistance-switching device is directly connected to a word line and the second terminal of the right resistance-switching device is directly connected to a bit line. ### Claim 14 (depends on 13) The method according to claim 13, further comprising: applying a first voltage bias at a gate of the transistor, wherein a drain of the transistor is connected to the internal node; and removing the first voltage bias after a second predetermined time. ### Claim 15 (depends on 13) The method according to claim 13, further comprising: monitoring the internal node to determine an internal node voltage by applying a first voltage bias at a gate of the transistor; and determining that the predetermined time is a time that the internal node voltage crosses half of the write voltage. ### Claim 16 A method for determining a logic level of a hybrid memory cell of a resistive random-access memory (ReRAM), the method comprising: applying a read voltage between a second terminal of a left resistance-switching device and a second terminal of a right resistance-switching device, wherein a first terminal of the left resistance-switching device is connected to a first terminal of the right resistance-switching device at an internal node; applying a voltage bias at a gate of a transistor, wherein a drain of the transistor is connected to the internal node; and sensing voltage at the internal node via a source of the transistor; wherein the hybrid memory cell comprises the left resistance-switching device, the right resistance-switching device, and the transistor. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: comparing the sensed voltage to a threshold voltage; determining that the logic level of the hybrid memory cell is logic ‘1’ when the sensed voltage is greater than the threshold voltage; and determining that the logic level of the hybrid memory cell is logic ‘0’ when the sensed voltage is less than the threshold voltage. ### Claim 18 (depends on 17) The method according to claim 17, wherein the threshold voltage is the read voltage divided by 2. ### Claim 19 (depends on 16) The method according to claim 16, wherein the logic level of the hybrid memory cell is based on a ratio of resistances of the right resistance-switching device and the left resistance-switching device. ### Claim 20 (depends on 16) The method according to claim 16, wherein the transistor is a minimum sized transistor.