# US 11,444,123 B2 · Selector transistor with metal replacement gate wordline

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- Number: US 11,444,123 B2
- Document ID: US11444123B2
- Status: Granted
- Kind: B2
- Application number: 16/898,234
- Filed: 2020-06-10
- Published: 2021-12-16
- Granted: 2022-09-13
- Earliest claimed: 2020-06-10
- Assignees: Integrated Silicon Solution, (Cayman) Inc.
- Applicants: Integrated Silicon Solution, (Cayman) Inc.
- Inventors: Dafna Beery; Peter Cuevas; Amitay Levi; Andrew J. Walker
- Web page: https://patentgrep.com/patent/US11444123B2

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/80: characterised by the materials
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

## Claims

### Claim 1

A method for manufacturing a memory array, the method comprising:
providing a semiconductor substrate;
depositing a first dielectric layer over the semiconductor substrate;
depositing a sacrificial layer over the first dielectric layer;
depositing a second dielectric layer over the sacrificial layer;
forming a plurality of vertical semiconductor columns in the sacrificial layer, the plurality of semiconductor columns extending to the substrate having a plurality of corresponding beveled recesses and each semiconductor column including a source and drain;
removing the sacrificial layer to form an open space adjacent to the semiconductor column;
depositing a protective and adhesion layer over the open space adjacent to the semiconductor column, the protective and adhesion layer coating the first dielectric layer and the second dielectric layer surrounding the open space; and
filling the open space with an electrically conductive metal.

### Claim 2 (depends on 1)

The method as in claim 1, wherein the sacrificial layer comprises silicon nitride.

### Claim 3 (depends on 1)

The method as in claim 1, wherein the electrically conductive metal comprises tungsten.

### Claim 4 (depends on 1)

The method as in claim 1, further comprising, before forming the semiconductor columns, forming an opening in the first and second dielectric layers and the sacrificial layer and then depositing a thin gate dielectric layer into the opening.

### Claim 5 (depends on 1)

The method as in claim 1, further comprising, after removing the sacrificial layer and before depositing the protective and adhesion layer, depositing a gate dielectric layer.

### Claim 6 (depends on 5)

The method as in claim 5, wherein the gate dielectric layer is one or more of silicon oxide and hafnium oxide.

### Claim 7 (depends on 1)

The method as in claim 1, wherein the sacrificial layer is removed by wet etch, and the method further comprises, after forming the semiconductor columns and before removing the sacrificial layer, performing a masking and etching process to remove a region of the second dielectric layer to facilitate removal of the sacrificial layer by wet etch.

### Claim 8 (depends on 1)

The method as in claim 1, wherein the sacrificial layer is removed by wet etch, and the method further comprises, after forming the semiconductor columns and before removing the sacrificial layer, performing a masking and etching process to remove a portion of the second dielectric layer and the sacrificial layer to facilitate removal of the sacrificial layer by wet etch.

### Claim 9 (depends on 1)

The method as in claim 1, further comprising forming a two terminal memory element, the two terminal memory element being electrically connected with the semiconductor column.

### Claim 10 (depends on 1)

The method as in claim 1, wherein the protective and adhesion layer comprises TiN.

### Claim 11

A method for manufacturing a vertical transistor structure, the method comprising:
providing a substrate;
depositing a first dielectric layer on the substrate;
depositing a layer of metal on the first dielectric layer;
depositing a second dielectric layer on the layer of metal;
forming an opening in the second dielectric layer, layer of metal and first dielectric layer, the opening extending to the substrate, the opening having a beveled recess extending to the substrate; and
forming a semiconductor pillar and a surrounding gate dielectric layer into the opening, the semiconductor pillar being formed by selective epitaxial growth and having a source region and a drain region.

### Claim 12 (depends on 11)

The method as in claim 11, further comprising, after depositing the first dielectric layer and before depositing the layer of metal, depositing a layer of TiN.

### Claim 13 (depends on 11)

The method as in claim 11, wherein the layer of metal comprises tungsten.

### Claim 14

A memory device comprising:
semiconductor column formed on a semiconductor substrate;
a gate dielectric layer surrounding the semiconductor column;
an electrically conductive metal gate line surrounding the gate dielectric layer and the semiconductor column; and
a two terminal resistive memory element electrically connected with the semiconductor column,
wherein the electrically conductive metal gate line is located between first and second dielectric layers, and the memory device further comprises a uniform TiN layer separating the electrically conductive metal gate line from the first and second dielectric layers and the gate dielectric layer.

### Claim 15 (depends on 14)

The memory device as in claim 14, wherein the electrically conductive metal gate line comprises tungsten.

### Claim 16 (depends on 14)

The memory device as in claim 14, wherein the semiconductor column comprises an epitaxially grown semiconductor.

### Claim 17 (depends on 14)

The memory device as in claim 14, wherein the semiconductor column comprises epitaxially grown semiconductor, the epitaxially grown semiconductor comprising one or more of silicon, silicon-germanium, gallium-arsenide, indium-gallium-arsenide or gallium indium zinc oxide.

### Claim 18 (depends on 14)

The memory device as in claim 14, further comprising a doped region in the semiconductor substrate, and wherein the semiconductor column is formed on the doped region in the semiconductor substrate.