# US 11,444,122 B2 · Semiconductor memory device and semiconductor memory manufacturing apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,122 B2 - Document ID: US11444122B2 - Status: Granted - Kind: B2 - Application number: 16/989,875 - Filed: 2020-08-10 - Published: 2020-11-26 - Granted: 2022-09-13 - Earliest claimed: 2017-08-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jae hoon Kim - Web page: https://patentgrep.com/patent/US11444122B2 ## CPC - H10B 61/22: {of the field-effect transistor [FET] type} - C23C 14/04: Coating on selected surface areas, e.g. using masks - C23C 14/042: {using masks} - C23C 14/225: {Oblique incidence of vaporised material on substrate} - C23C 14/34: Sputtering - C23C 14/3407: {Cathode assembly for sputtering apparatus, e.g. Target} - C23C 14/3464: {using more than one target (C23C14/56 takes precedence)} - C23C 14/50: Substrate holders - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - H01F 10/3286: {Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy} - H01J 37/3411: {Constructional aspects of the reactor} - H01J 37/3441: {Dark space shields} - H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements} - H10N 50/01: Manufacture or treatment - H10N 50/10: Magnetoresistive devices - H10N 50/80: Constructional details - H10N 50/85: Materials of the active region - H01F 10/123: {having a L10 crystallographic structure, e.g. [Co,Fe][Pt,Pd] thin films} - H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]} - H10B: ELECTRONIC MEMORY DEVICES - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - G11C: STATIC STORES (semiconductor memory devices H10B) - H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell. ## Claims ### Claim 1 A semiconductor memory manufacturing apparatus comprising: a wafer holder configured to support a semiconductor wafer; a sputtering target holder obliquely located above the wafer holder; and a shielding plate interposed between the sputtering target holder and the wafer holder, wherein the shielding plate includes a first exposure area and a second exposure area, wherein the first exposure area is larger than the second exposure area, and wherein the shielding plate is spaced apart from the sputtering target holder and is disposed closer to the wafer holder than the sputtering target holder. ### Claim 2 (depends on 1) The semiconductor memory manufacturing apparatus of claim 1, wherein the shielding plate includes a first exposure hole in the first exposure area and a plurality of second exposure holes in the second exposure area. ### Claim 3 (depends on 2) The semiconductor memory manufacturing apparatus of claim 2, wherein: the shielding plate includes a plurality of shielding bars in the second exposure area; the plurality of shielding bars are extended in a first direction and are spaced apart from each other in a second direction; and the plurality of second exposure holes that are divided by the plurality of shielding bars are arranged in a line shape which extends in the first direction and are spaced apart from each other in the second direction. ### Claim 4 (depends on 3) The semiconductor memory manufacturing apparatus of claim 3, wherein a width of each of the plurality of shielding bars, a separation distance between two adjacent shielding bars of the plurality of shielding bars, or a separation height of the shielding plate from an upper surface of the semiconductor wafer are controlled such that a deposition layer to be deposited on the semiconductor wafer has a predetermined thickness. ### Claim 5 (depends on 3) The semiconductor memory manufacturing apparatus of claim 3, wherein each of the plurality of shielding bars has a width between 5 μm and 50 μm. ### Claim 6 (depends on 3) The semiconductor memory manufacturing apparatus of claim 3, wherein two adjacent shielding bars of the plurality of shielding bars are separated at a distance between 50 μm and 500 μm. ### Claim 7 (depends on 3) The semiconductor memory manufacturing apparatus of claim 3, wherein the shielding plate is distant from an upper surface of the semiconductor wafer at a distance between 0.5 cm to 1.0 cm. ### Claim 8 (depends on 2) The semiconductor memory manufacturing apparatus of claim 2, wherein the second exposure area includes: a plurality of first shielding bars extended in a first direction and spaced apart from each other in a second direction; and a plurality of second shielding bars extended in the second direction and spaced apart from each other in the first direction, and wherein the plurality of first shielding bars and the plurality of second shielding bars are connected to each other to form a grid shape having the plurality of second exposure holes each of which has a rectangular shape. ### Claim 9 (depends on 1) The semiconductor memory manufacturing apparatus of claim 1, wherein the shielding plate is configured to rotate. ### Claim 10 A semiconductor memory manufacturing apparatus comprising: a wafer holder configured to support a semiconductor wafer including a first memory area and a second memory area; a sputtering target holder obliquely located above the wafer holder; and a shielding plate interposed between the sputtering target holder and the wafer holder, wherein the shielding plate includes a first exposure area located above the first memory area, and a second exposure area located above the second memory area, wherein the first exposure area is larger than the second exposure area, wherein a first memory device is located in the first memory area, wherein a second memory device is located in the second memory area, and wherein the shielding plate is spaced apart from the sputtering target holder and is disposed closer to the wafer holder than the sputtering target holder. ### Claim 11 (depends on 10) The semiconductor memory manufacturing apparatus of claim 10, wherein the first memory device operates with smaller energy, and higher speed than the second memory device. ### Claim 12 (depends on 11) The semiconductor memory manufacturing apparatus of claim 11, wherein the first memory device is formed as SRAM or DRAM, and wherein the second memory device is formed as flash memory. ### Claim 13 (depends on 10) The semiconductor memory manufacturing apparatus of claim 10, wherein the first memory device includes a first magnetoresistive cell, and wherein the second memory device includes a second magnetoresistive cell. ### Claim 14 (depends on 13) The semiconductor memory manufacturing apparatus of claim 13, wherein each magnetoresistive cell includes a fixed layer, a tunnel barrier layer, a free layer, and a capping layer, wherein the fixed layer, the tunnel barrier layer, and the free layer form a magnetic tunnel junction (MTJ). ### Claim 15 (depends on 14) The semiconductor memory manufacturing apparatus of claim 14, wherein a thickness of the capping layer of the second magnetoresistive cell is thinner than a thickness of the capping layer of the first magnetoresistive cell. ### Claim 16 (depends on 14) The semiconductor memory manufacturing apparatus of claim 14, wherein a first layer of a plurality of layers of the first magnetoresistive cell has a substantially uniform thickness, wherein a second layer which corresponding to the first layer of the plurality of layers of the second magnetoresistive cell has a substantially uniform thickness, and wherein the thickness of the second layer is thinner than the thickness of the first layer. ### Claim 17 (depends on 10) The semiconductor memory manufacturing apparatus of claim 10, wherein the shielding plate includes a plurality of shielding bars in the second exposed area, and wherein a width of each shielding bar is smaller than a separation distance between the plurality of shielding bars. ### Claim 18 (depends on 17) The semiconductor memory manufacturing apparatus of claim 17, wherein each shielding bar has a shape extending in one direction. ### Claim 19 (depends on 17) The semiconductor memory manufacturing apparatus of claim 17, wherein the shielding plate further includes a shielding frame which surrounds the outside of the plurality of shielding bars, and has ring shape, and wherein an inner region of the shielding frame has an area larger than that of the semiconductor wafer. ### Claim 20 A semiconductor memory manufacturing apparatus comprising: a process chamber in which a sputtering process is performed; a wafer holder located inside the process chamber and configured to support and rotate a semiconductor wafer including a first memory area and a second memory area; a sputtering target obliquely located above the semiconductor wafer inside the process chamber so that sputtering particles are obliquely incident on an upper surface of the semiconductor wafer during the sputtering process; and a shielding plate fixed to an upper portion of the wafer holder, configured to rotate with the wafer holder, and including a plurality of first exposure areas and second exposure areas, wherein the first exposure areas are located on the first memory area, the second exposure areas are located on the second memory area, and each of the first exposure areas has an exposure area per unit area larger than that of each of the second exposure areas, wherein each of the first exposure areas includes a first exposure hole to vertically pass through an entire area thereof, and wherein each of the second exposure areas includes a plurality of second exposure holes to vertically pass therethrough.