# US 11,444,116 B2 · Method for forming image sensor

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- Number: US 11,444,116 B2
- Document ID: US11444116B2
- Status: Granted
- Kind: B2
- Application number: 17/135,590
- Filed: 2020-12-28
- Published: 2021-04-22
- Granted: 2022-09-13
- Earliest claimed: 2015-09-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Wei Chia; Chun-Hao Chou; Kai-Chun Hsu; Kuo-Cheng Lee; Shyh-Fann Ting
- Web page: https://patentgrep.com/patent/US11444116B2

## CPC

- H10F 39/014: {of CMOS image sensors}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.

## Claims

### Claim 1

A method comprising:
depositing a gate dielectric layer over a substrate;
sequentially depositing a gate electrode layer, a protection oxide layer, and a hard mask over the gate dielectric layer;
patterning the gate electrode layer and the protection oxide layer by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer; and
performing an etching process to remove the hard mask and thin the protection oxide layer after forming the gate structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate electrode layer is made of polysilicon.

### Claim 3 (depends on 1)

The method of claim 1, wherein the hard mask is made of nitride.

### Claim 4 (depends on 1)

The method of claim 1, further comprising oxidizing a portion of the gate electrode layer of the gate structure prior to performing the etching process.

### Claim 5 (depends on 1)

The method of claim 1, wherein patterning the gate electrode layer and the protection oxide layer comprises forming a recess in the gate dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the protection oxide layer is thinner than the hard mask.

### Claim 7 (depends on 1)

The method of claim 1, wherein sequentially depositing the gate electrode layer, the protection oxide layer, and the hard mask over the gate dielectric layer is such that the protection oxide layer is in contact with the gate electrode layer.

### Claim 8

A method comprising:
depositing a gate dielectric layer over a substrate;
depositing a gate electrode layer over the gate dielectric layer;
depositing a protection oxide layer over the gate electrode layer;
depositing a hard mask over the protection oxide layer;
pattering the gate dielectric layer, the gate electrode layer, the protection oxide layer, and the hard mask such that the gate dielectric layer comprises a first portion directly under the patterned gate electrode layer and a second portion spaced apart from the gate electrode layer, and the first portion is thicker than the second portion; and
forming an oxide layer on a sidewall of the patterned gate electrode layer and in contact with a top surface of the first portion of the gate dielectric layer and a bottom surface of the protection oxide layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the oxide layer is such that the oxide layer is spaced apart from the second portion of the gate dielectric layer.

### Claim 10 (depends on 8)

The method of claim 8, further comprising removing the hard mask after forming the oxide layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing a portion of the protection oxide layer after removing the hard mask.

### Claim 12 (depends on 8)

The method of claim 8, wherein forming the oxide layer is such that the oxide layer is thinner than the protection oxide layer.

### Claim 13 (depends on 8)

The method of claim 8, wherein forming the oxide layer is such that the protection oxide layer covers a portion of the oxide layer.

### Claim 14 (depends on 8)

The method of claim 8, wherein the hard mask and the protection oxide layer comprise different materials.

### Claim 15

A method comprising:
depositing a gate dielectric layer over a substrate;
forming a gate structure over the gate dielectric layer, wherein the gate structure comprises:
a gate electrode over the gate dielectric layer;
a protection oxide layer over the gate electrode; and
a hard mask over the protection oxide layer;
forming a recess in the gate dielectric layer after forming the gate structure; and
forming an oxide layer on a sidewall of the gate electrode, such that a first portion of the oxide layer is in contact with a portion of the gate dielectric layer and a second portion of the oxide layer overhangs above the recess of the gate dielectric layer, wherein forming the oxide layer is such that a top surface of the first portion of the oxide layer is in contact with the protection oxide layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising removing the hard mask of the gate structure after forming the oxide layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein after removing the hard mask of the gate structure, the protection oxide layer covers the first portion of the oxide layer but spaced apart from the second portion of the oxide layer.

### Claim 18 (depends on 16)

The method of claim 16, further comprising reducing a thickness of the protection oxide layer after removing the hard mask of the gate structure.

### Claim 19 (depends on 15)

The method of claim 15, wherein a bottom surface of the oxide layer is substantially coplanar with a bottom surface of the gate electrode.

### Claim 20 (depends on 15)

The method of claim 15, wherein the hard mask and the protection oxide layer comprise different materials.