# US 11,444,105 B2 · Array substrate and manufacturing method thereof

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- Number: US 11,444,105 B2
- Document ID: US11444105B2
- Status: Granted
- Kind: B2
- Application number: 16/621,238
- Filed: 2019-11-04
- Published: 2020-12-31
- Granted: 2022-09-13
- Earliest claimed: 2019-06-21
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Suping Xi
- Web page: https://patentgrep.com/patent/US11444105B2

## CPC

- G02F 1/134345: {Subdivided pixels, e.g. for grey scale or redundancy}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13624: {having more than one switching element per pixel}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G02F 1/133707: {Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes}
- G02F 2201/40: Arrangements for improving the aperture ratio
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides an array substrate and a manufacturing method thereof, an array substrate includes a sub-pixel including a main-region and a sub-region. A gate line is disposed between the main-region and the sub-region, and two adjacent data lines define a pixel boundary. A transparent common electrode line is respectively disposed corresponding to the main-region and the sub-region. Wherein, a projection range of the pixel electrode on the substrate covers a projection range of part of the transparent common electrode line corresponding to a direction of the data line on the substrate.

## Claims

### Claim 1

An array substrate, comprising:
a plurality of sub-pixels disposed on a substrate in an array, each of the sub-pixels comprising a main-region and a sub-region, wherein each of the sub-pixels comprises a main-region thin film transistor, a sub-region thin film transistor, and a shared thin film transistor;
a gate line disposed corresponding to each row of the sub-pixels and disposed between the main-region and the sub-region, a data line disposed corresponding to each column of the sub-pixels, and two adjacent data lines defining a pixel boundary;
a transparent common electrode line disposed on a same layer as the gate line and respectively disposed corresponding to the main-region and the sub-region; and
a pixel electrode comprising a main-region pixel electrode disposed corresponding to the main-region and a sub-region pixel electrode disposed corresponding to the sub-region, wherein both the main-region pixel electrode and the sub-region pixel electrode have a rectangular external contour, and the main-region pixel electrode is connected to a drain of the main-region thin film transistor through a through-hole, and the sub-region pixel electrode is connected to a drain of the sub-region thin film transistor through another through-hole;
wherein a projection range of the pixel electrode on the substrate at least covers a projection range of a part of the transparent common electrode line corresponding to the data line on the substrate and covers a projection range of the through-holes on the substrate; and
wherein the main-region comprises a main-region storage electrode, the main-region storage electrode and a part of the transparent common electrode line corresponding to the main-region are insulated by a dielectric layer and form a main-region storage capacitor; and
the sub-region comprises a sub-region storage electrode, and the sub-region storage electrode and a part of the transparent common electrode line corresponding to the sub-region are insulated by the dielectric layer and form a sub-region storage capacitor.

### Claim 2 (depends on 1)

The array substrate as claimed in claim 1, wherein the projection range of the pixel electrode on the substrate further covers a projection range of a part of the transparent common electrode line corresponding to the gate line on the substrate.

### Claim 3 (depends on 1)

The array substrate as claimed in claim 1, wherein both a projection of the main-region storage electrode on the substrate and a projection of the sub-region storage electrode on the substrate are formed in the projection range of the pixel electrode on the substrate.

### Claim 4

An array substrate, comprising:
a plurality of sub-pixels disposed on a substrate in an array, each of the sub-pixels comprising a main-region and a sub-region, wherein each of the sub-pixels comprises a main-region thin film transistor, a sub-region thin film transistor, and a shared thin film transistor;
a gate line disposed corresponding to each row of the sub-pixels and disposed between the main-region and the sub-region, a data line disposed corresponding to each column of the sub-pixels, and two adjacent data lines defining a pixel boundary;
a transparent common electrode line disposed on a same layer as the gate line and respectively disposed corresponding to the main-region and the sub-region; and
a pixel electrode comprising a main-region pixel electrode disposed corresponding to the main-region and a sub-region pixel electrode disposed corresponding to the sub-region, wherein both the main-region pixel electrode and the sub-region pixel electrode have a rectangular external contour, and the main-region pixel electrode is connected to a drain of the main-region thin film transistor through a through-hole, and the sub-region pixel electrode is connected to a drain of the sub-region thin film transistor through another through-hole, and the pixel electrode is a transparent electrode;
wherein a projection range of the pixel electrode on the substrate at least covers a projection range of a part of the transparent common electrode line corresponding to the data line on the substrate and covers a projection range of the through-holes on the substrate;
wherein the main-region comprises a main-region storage electrode, the main-region storage electrode and a part of the transparent common electrode line corresponding to the main-region storage electrode are insulated by a dielectric layer and form a main-region storage capacitor; and
the sub-region comprises a sub-region storage electrode, and the sub-region storage electrode and a part of the transparent common electrode line corresponding to the sub-region storage electrode are insulated by the dielectric layer and form a sub-region storage capacitor.

### Claim 5 (depends on 4)

The array substrate as claimed in claim 4, wherein the projection range of the pixel electrode on the substrate further covers a projection range of a part of the transparent common electrode line corresponding to the gate line on the substrate.

### Claim 6 (depends on 4)

The array substrate as claimed in claim 4, wherein both a projection of the main-region storage electrode on the substrate and a projection of the sub-region storage electrode on the substrate are formed in the projection range of the pixel electrode on the substrate.