# US 11,444,103 B2 · Array substrate and method of manufacturing thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,103 B2
- Document ID: US11444103B2
- Status: Granted
- Kind: B2
- Application number: 16/637,873
- Filed: 2019-11-08
- Published: 2022-02-03
- Granted: 2022-09-13
- Earliest claimed: 2019-08-20
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Bingkun Yin
- Web page: https://patentgrep.com/patent/US11444103B2

## CPC

- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 86/021: {of multiple TFTs}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate and a method of manufacturing thereof are provided. The array substrate includes a substrate, a buffer layer, a plurality of thin film transistors, an organic layer, and a first electrode. By defining a via hole between two adjacent thin film transistors in the bending region, the via hole penetrates through the passivation layer, the gate insulating layer, and the first metal trace, which can effectively reduce stress between the passivation layer and the gate insulating layer.

## Claims

### Claim 1

An array substrate, comprising a display region and at least one bending region, wherein the array substrate comprises:
a substrate
a buffer layer disposed on the substrate;
a thin film transistor layer disposed on the buffer layer away from the substrate, wherein the thin film transistor layer comprises a first metal trace, a plurality of thin film transistors are formed in the thin film transistor layer, and wherein in the at least one bending region, the array substrate further comprises at least one via hole and two adjacent thin film transistors, the at least one via hole is defined between the two adjacent thin film transistors, and the via hole penetrates through the first metal trace to a surface of the buffer layer; and
an organic layer disposed on the thin film transistor layer, wherein the via hole is filled with the organic layer, and the via hole corresponds to the bending region.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein material of the organic layer comprises a photoresist, and material of the buffer layer comprises silicon nitride or silicon oxide.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein the substrate comprises a glass substrate and a transparent base layer, and the transparent base layer is disposed on a side of the glass substrate close to the buffer layer.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein the first metal trace is disposed on a side of the buffer layer away from the substrate, and the thin film transistor layer further comprises:
a gate insulating layer disposed on the first metal trace;
a semiconductor layer disposed on a side of the gate insulating layer away from the first metal trace;
a second metal trace disposed on the semiconductor layer and the gate insulating layer; and
a passivation layer disposed on the second metal trace, the semiconductor layer, and the gate insulating layer.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein material of the semiconductor layer comprises indium gallium zinc oxide, the second metal trace comprises a source trace and a drain trace, and the source trace and the drain trace are respectively connected to the semiconductor layer.

### Claim 6 (depends on 4)

The array substrate according to claim 4, further comprising a first electrode, wherein the first electrode is disposed on the organic layer, and the first electrode is connected to the second metal trace.

### Claim 7 (depends on 1)

The array substrate according to claim 1, wherein the first metal trace comprises a plurality of hollow holes, and the plurality of hollow holes are defined by the via hole penetrating the first metal trace.

### Claim 8 (depends on 7)

The array substrate according to claim 7, wherein a shape of each of the hollow holes comprises a circle or a square, and the hollow holes are evenly distributed on the first metal trace.

### Claim 9 (depends on 7)

The array substrate according to claim 7, wherein a diameter of each of the hollow holes is 3 to 5 μm.

### Claim 10

A method of manufacturing an array substrate, comprising following steps:
providing a glass substrate, wherein a transparent base layer is coated on the glass substrate, a substrate is formed through pre-baking and solid-baking, and the substrate comprises at least one bending region and a display region;
depositing a buffer layer on the substrate;
depositing a first metal trace on a side of the buffer layer away from the substrate;
depositing a gate insulating layer on the first metal trace;
depositing a semiconductor layer on a side of the gate insulating layer away from the first metal trace;
depositing a second metal trace on the semiconductor layer and the gate insulating layer;
depositing a passivation layer on the second metal trace, the semiconductor layer, and the gate insulating layer;
defining at least one via hole and two adjacent thin film transistors in the bending region, wherein the at least one via hole is defined between the two adjacent thin film transistors, and the at least one via hole penetrates through the passivation layer, the gate insulating layer, and the first metal trace to a surface of the buffer layer;
depositing an organic layer on the passivation layer and in the via hole; and
depositing a first electrode on the organic layer, wherein the first electrode is connected to the second metal trace.