# US 11,444,102 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,102 B2 - Document ID: US11444102B2 - Status: Granted - Kind: B2 - Application number: 17/185,179 - Filed: 2021-02-25 - Published: 2021-06-17 - Granted: 2022-09-13 - Earliest claimed: 2015-03-09 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takeshi Kamigaichi - Web page: https://patentgrep.com/patent/US11444102B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10B 43/30: characterised by the memory core region - H10B 43/35: with cell select transistors, e.g. NAND - H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 64/252: {for vertical or pseudo-vertical devices} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part. ## Claims ### Claim 1 A semiconductor device comprising: a stacked body including a plurality of electrode layers stacked with an insulator interposed and a source-side select gate layer provided below the electrode layers, a hole extending in a stacking direction of the stacked body through the stacked body and having a central axis along the stacking direction; a semiconductor body extending in the stacking direction in the hole and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers; and a columnar insulating member provided inside the semiconductor body having the pipe shape at the intersecting portions of the semiconductor body with the electrode layers and at an intersecting portion of the semiconductor body with the source-side select gate layer, the electrode layers including a first electrode layer and a second electrode layer, the insulator including a first insulator contiguous above the first electrode layer, a second insulator contiguous below the first electrode layer, a third insulator contiguous above the second electrode layer, and a fourth insulator contiguous below the second electrode layer, the first electrode layer being interposed between the first insulator and the second insulator, the second electrode layer being interposed between the third insulator and the fourth insulator, an outer periphery of the semiconductor body having a first outer periphery facing to the first insulator, a second outer periphery facing to the second insulator, a first base surface facing to the first electrode layer, a third outer periphery facing to the third insulator, a fourth outer periphery facing to the fourth insulator, and a second base surface facing to the second electrode layer, the first base surface being disposed between the first outer periphery and the second outer periphery and being defined by a surface substantially aligned in the stacking direction with the first outer periphery and the second outer periphery, the second base surface being disposed between the third outer periphery and the fourth outer periphery and being defined by a surface substantially aligned in the stacking direction with the third outer periphery and the fourth outer periphery, a distance from the central axis to the first base surface being larger than a distance from the central axis to the second base surface, a distance between the first base surface and the first electrode layer being larger than a distance between the second base surface and the second electrode layer. ### Claim 2 (depends on 1) The device according to claim 1, further comprising a stacked film between the semiconductor body and the electrode layers in the hole. ### Claim 3 (depends on 2) The device according to claim 2, wherein the stacked film includes a silicon oxide film on a side of the semiconductor body and a silicon nitride film between the silicon oxide film and the electrode layers. ### Claim 4 (depends on 1) The device according to claim 1, wherein the memory cells include a tunnel insulating film, a charge storage film, and a block insulating film stacked at the intersecting portions in order on the outer periphery of the semiconductor body. ### Claim 5 (depends on 4) The device according to claim 4, wherein a block insulating film includes a silicon oxide film and a film having higher dielectric constant than the silicon oxide film. ### Claim 6 (depends on 1) The device according to claim 1, wherein the memory cells include a tunnel insulating film and a charge storage film formed along the outer periphery of the semiconductor body, the tunnel insulating film and the charge storage film extending in the stacking direction between the semiconductor body and the second electrode layer, between the semiconductor body and the third insulator, and between the semiconductor body and the fourth insulator. ### Claim 7 (depends on 1) The device according to claim 1, wherein the columnar insulating member is formed as one body inside an intersecting portion of the semiconductor body with a lowermost electrode layer of the electrode layers and inside the intersecting portion of the semiconductor body with the source-side select gate layer. ### Claim 8 (depends on 1) The device according to claim 1, wherein the first electrode layer is disposed above the second electrode layer in the stacking direction. ### Claim 9 (depends on 1) The device according to claim 1, wherein a thickness of the first electrode layer is substantially equal to a thickness of the second electrode layer. ### Claim 10 (depends on 9) The device according to claim 9, wherein a thickness of the first electrode layer is greater than both of a thickness of the first insulator and a thickness of the second insulator and a thickness of the second electrode layer is greater than both of a thickness of the third insulator and a thickness of the fourth insulator. ### Claim 11 A semiconductor device comprising: a stacked body including a plurality of electrode layers stacked with an insulator interposed and a source-side select gate layer provided below the electrode layers, a hole extending in a stacking direction of the stacked body through the stacked body and having a central axis along the stacking direction; a semiconductor body extending in the stacking direction in the hole and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers; and a columnar insulating member provided inside the semiconductor body having the pipe shape at the intersecting portions of the semiconductor body with the electrode layer and at an intersecting portion of the semiconductor body with the source-side select gate layer, the electrode layers including a first electrode layer and a second electrode layer, the insulator including a first insulator contiguous above the first electrode layer, a second insulator contiguous below the first electrode layer, a third insulator contiguous above the second electrode layer, and a fourth insulator contiguous below the second electrode layer, the first electrode layer being interposed between the first insulator and the second insulator, the second electrode layer being interposed between the third insulator and the fourth insulator, a thickness of the first electrode layer being greater than both of a thickness of the first insulator and a thickness of the second insulator, an outer periphery of the semiconductor body having a first outer periphery facing to the first insulator, a second outer periphery facing to the second insulator, a first base surface facing to the first electrode layer, a third outer periphery facing to the third insulator, a fourth outer periphery facing to the fourth insulator, and a second base surface facing to the second electrode layer, the first base surface being disposed between the first outer periphery and the second outer periphery and being defined by a surface substantially aligned in the stacking direction with the first outer periphery and the second outer periphery, the second base surface being disposed between the third outer periphery and the fourth outer periphery and being defined by a surface substantially aligned in the stacking direction with the third outer periphery and the fourth outer periphery, a distance from the central axis to the first base surface being larger than a distance from the central axis to the second base surface, a distance between the first base surface and the first electrode layer being larger than a distance between the second base surface and the second electrode layer. ### Claim 12 (depends on 11) The device according to claim 11, further comprising a stacked film between the semiconductor body and the electrode layers in the hole. ### Claim 13 (depends on 12) The device according to claim 12, wherein the stacked film includes a silicon oxide film on a side of the semiconductor body and a silicon nitride film between the silicon oxide film and the electrode layers. ### Claim 14 (depends on 11) The device according to claim 11, wherein the memory cells include a tunnel insulating film, a charge storage film, and a block insulating film stacked at the intersecting portions in order on the outer periphery of the semiconductor body. ### Claim 15 (depends on 14) The device according to claim 14, wherein a block insulating film includes a silicon oxide film and a film having higher dielectric constant than the silicon oxide film. ### Claim 16 (depends on 11) The device according to claim 11, wherein the memory cells include a tunnel insulating film and a charge storage film formed along the outer periphery of the semiconductor body, the tunnel insulating film and the charge storage film extending in the stacking direction between the semiconductor body and the second electrode layer, between the semiconductor body and the third insulator, and between the semiconductor body and the fourth insulator. ### Claim 17 (depends on 11) The device according to claim 11, wherein the columnar insulating member is formed as one body inside an intersecting portion of the semiconductor body with a lowermost electrode layer of the electrode layers and inside the intersecting portion of the semiconductor body with the source-side select gate layer. ### Claim 18 (depends on 11) The device according to claim 11, wherein the first electrode layer is disposed above the second electrode layer in the stacking direction. ### Claim 19 (depends on 11) The device according to claim 11, wherein a thickness of the first electrode layer is substantially equal to a thickness of the second electrode layer. ### Claim 20 (depends on 11) The device according to claim 11, wherein a thickness of the second electrode layer is greater than both of a thickness of the third insulator and a thickness of the fourth insulator.