# US 11,444,100 B2 · Vertical memory device with tri-layer channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,100 B2 - Document ID: US11444100B2 - Status: Granted - Kind: B2 - Application number: 16/957,579 - Filed: 2018-11-19 - Published: 2020-10-15 - Granted: 2022-09-13 - Earliest claimed: 2018-06-08 - Assignees: Industry-University Cooperation Foundation Hanyang University - Applicants: Industry-University Cooperation Foundation Hanyang University - Inventors: Tae Whan Kim; Jun Gyu Lee; Hyun Soo Jung - Web page: https://patentgrep.com/patent/US11444100B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A vertical memory device and a method of fabricating the same are proposed. The vertical memory device includes a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate; a channel structure extending in the first direction from the substrate to penetrate the gate stack structure; and charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure. ## Claims ### Claim 1 A vertical memory device, comprising: a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate; a channel structure extending in the first direction from the substrate to penetrate the gate stack structure; and charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure, wherein the channel structure comprises an insulating pillar formed at a center thereof and channel layers formed to surround the insulating pillar, wherein each of the channel layers comprises an undoped channel area, an n-type doped buried channel area formed to surround the undoped channel area, and a p-type doped barrier area formed to surround the n-type doped buried channel area. ### Claim 2 (depends on 1) The vertical memory device according to claim 1, wherein the n-type doped buried channel area increases an on-current level of the vertical memory device and decreases a pass voltage (Vpass) required during a word line read operation. ### Claim 3 (depends on 1) The vertical memory device according to claim 1, wherein the p-type doped barrier area induces Frenkel-Poole tunneling to increase a transferable distance of electrons. ### Claim 4 (depends on 1) The vertical memory device according to claim 1, wherein a thickness of each of the channel layers is equal to a sum of a thickness of the undoped channel area, a thickness of the n-type doped buried channel area, and a thickness of the p-type doped barrier area. ### Claim 5 (depends on 1) The vertical memory device according to claim 1, wherein the thickness of the n-type doped buried channel area is 5 nm to 8 nm. ### Claim 6 (depends on 1) The vertical memory device according to claim 1, wherein the thickness of the p-type doped barrier area is 3 nm to 5 nm. ### Claim 7 (depends on 1) The vertical memory device according to claim 1, wherein the n-type doped buried channel area is doped in a doping concentration of 1×1019 atoms/cm3. ### Claim 8 (depends on 1) The vertical memory device according to claim 1, wherein the p-type doped barrier area is doped in a doping concentration of 1×1019 atoms/cm3. ### Claim 9 (depends on 1) The vertical memory device according to claim 1, wherein the first ion implantation is performed using at least one n-type dopant of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). ### Claim 10 (depends on 1) The vertical memory device according to claim 1, wherein the second ion implantation is performed using at least one p-type dopant of boron (B), aluminum (Al), indium (In), and gallium (Ga). ### Claim 11 (depends on 1) The vertical memory device according to claim 1, wherein the channel layers are formed through an epitaxial process. ### Claim 12 (depends on 1) The vertical memory device according to claim 1, wherein each of the channel layers comprises at least one of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), and epitaxial silicon (epi-Si). ### Claim 13 (depends on 1) The vertical memory device according to claim 1, wherein each of the charge storage elements comprises a tunnel oxide film, a charge trap film, and a blocking insulating film. ### Claim 14 (depends on 13) The vertical memory device according to claim 13, wherein the tunnel oxide film comprises at least one of silicon oxides and metal oxides. ### Claim 15 (depends on 13) The vertical memory device according to claim 13, wherein the charge trap film comprises at least one of silicon nitrides and metal oxides. ### Claim 16 (depends on 13) The vertical memory device according to claim 13, wherein the blocking insulating film comprises at least one of silicon oxides and metal oxides.