# US 11,444,098 B2 · Vertical non-volatile memory devices and methods of programming the same

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- Number: US 11,444,098 B2
- Document ID: US11444098B2
- Status: Granted
- Kind: B2
- Application number: 16/850,244
- Filed: 2020-04-16
- Published: 2021-03-04
- Granted: 2022-09-13
- Earliest claimed: 2019-09-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Younghwan Son; Seungwon Lee; Seogoo Kang; Juyoung Lim; Jeehoon Han
- Web page: https://patentgrep.com/patent/US11444098B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 43/10: characterised by the top-view layout
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 50/283: {by chemical means}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

## Claims

### Claim 1

A vertical non-volatile memory device, comprising:
a channel on a substrate, the channel extending in a first direction perpendicular to an upper surface of the substrate;
a first charge storage structure on an outer sidewall of the channel;
a second charge storage structure on an inner sidewall of the channel;
first gate electrodes spaced apart from each other in the first direction on the substrate, each of the first gate electrodes surrounding the first charge storage structure; and
a second gate electrode on an inner sidewall of the second charge storage structure, wherein:
the channel has a ring shape in a plan view, and
the second gate electrode is disposed inside the ring shape of the channel and is completely encircled by the channel in the plan view.

### Claim 2 (depends on 1)

The vertical non-volatile memory device as claimed in claim 1, wherein:
the first charge storage structure includes a first tunnel insulation layer, a first charge storage layer, and a first blocking layer sequentially stacked from the outer sidewall of the channel, and
the second charge storage structure includes a second tunnel insulation layer, a second charge storage layer, and a second blocking layer sequentially stacked from the inner sidewall of the channel.

### Claim 3 (depends on 2)

The vertical non-volatile memory device as claimed in claim 2, wherein each of the first and second tunnel insulation layers includes silicon oxide, each of the first and second charge storage layers includes silicon nitride, and each of the first and second blocking layers includes silicon oxide.

### Claim 4 (depends on 2)

The vertical non-volatile memory device as claimed in claim 2, further comprising a third blocking layer between each of the first gate electrodes and the first charge storage structure, the third blocking layer including a metal oxide.

### Claim 5 (depends on 2)

The vertical non-volatile memory device as claimed in claim 2, wherein:
the second gate electrode includes a metal, and
a third blocking layer is disposed between the second gate electrode and the second charge storage structure, the third blocking layer including a metal oxide.

### Claim 6 (depends on 2)

The vertical non-volatile memory device as claimed in claim 2, wherein:
the second gate electrode includes polysilicon doped with impurities, and
the second gate electrode directly contacts the second charge storage structure.

### Claim 7 (depends on 1)

The vertical non-volatile memory device as claimed in claim 1, further comprising a conductive pad contacting an upper surface of the channel.

### Claim 8 (depends on 7)

The vertical non-volatile memory device as claimed in claim 7, wherein the conductive pad has a ring shape in the plan view.

### Claim 9 (depends on 8)

The vertical non-volatile memory device as claimed in claim 8, wherein the conductive pad has the ring shape including an elliptical outer contour and a circular inner contour in the plan view.

### Claim 10 (depends on 9)

The vertical non-volatile memory device as claimed in claim 9, wherein the conductive pad has the ring shape including a rectangular outer contour and a circular inner contour in the plan view.

### Claim 11 (depends on 7)

The vertical non-volatile memory device as claimed in claim 7, wherein the conductive pad does not contact the second gate electrode.

### Claim 12 (depends on 11)

The vertical non-volatile memory device as claimed in claim 11, further comprising:
a first bit line electrically connected to the conductive pad; and
a second bit line electrically connected to the second gate electrode.

### Claim 13 (depends on 12)

The vertical non-volatile memory device as claimed in claim 12, further comprising:
a first contact plug contacting an upper surface of the conductive pad and a bottom surface of the first bit line; and
a second contact plug contacting an upper surface of the second gate electrode and a bottom surface of the second bit line.

### Claim 14 (depends on 12)

The vertical non-volatile memory device as claimed in claim 12, wherein:
a plurality of first bit lines and a plurality of second bit lines are formed to be spaced apart from each other in a second direction parallel to the upper surface of the substrate, and
two of the plurality of first bit lines are disposed between neighboring ones of the plurality of second bit lines in the second direction.

### Claim 15 (depends on 14)

The vertical non-volatile memory device as claimed in claim 14, wherein:
each of the first gate electrodes extends in the second direction, and
each of the first and second bit lines extends in a third direction parallel to the upper surface of the substrate and crossing the second direction.

### Claim 16 (depends on 1)

The vertical non-volatile memory device as claimed in claim 1, wherein:
a plurality of channels is spaced apart from each other in a horizontal direction parallel to the upper surface of the substrate, and
a channel connection pattern is disposed under the first gate electrodes on the substrate, the channel connection pattern configured to connect the plurality of channels with each other.

### Claim 17 (depends on 16)

The vertical non-volatile memory device as claimed in claim 16, further comprising a support layer between the channel connection pattern and the first gate electrodes, the support layer including polysilicon doped with impurities.

### Claim 18 (depends on 1)

The vertical non-volatile memory device as claimed in claim 1, wherein:
the first charge storage structure includes an upper portion covering an outer sidewall of the channel and a lower portion covering a bottom surface of the channel, and
the second charge storage structure has a cupped shape.

### Claim 19

A vertical non-volatile memory device, comprising:
a channel on a substrate, the channel extending in a first direction perpendicular to an upper surface of the substrate and having a cup-like shape in a vertical cross-sectional view;
a first charge storage structure on an outer sidewall of the channel;
first gate electrodes spaced apart from each other in the first direction on the substrate, each of the first gate electrodes surrounding the first charge storage structure;
a second gate electrode in an inner space formed by the channel; and
a conductive pad having a ring shape, the conductive pad contacting an upper surface of the channel and not contacting an upper surface of the second gate electrode, wherein:
the channel has a ring shape in a plan view, the ring shape of the channel encircling the inner space formed by the channel, and
the second gate electrode is disposed inside the ring shape of the channel and is completely encircled by the channel in the plan view.

### Claim 20

A vertical non-volatile memory device, comprising:
a channel on a substrate, the channel extending in a first direction perpendicular to an upper surface of the substrate;
a first charge storage structure on an outer sidewall of the channel;
a second charge storage structure on an inner sidewall of the channel;
first gate electrodes spaced apart from each other in the first direction on the substrate, each of the first gate electrodes surrounding the first charge storage structure;
a second gate electrode on an inner sidewall of the second charge storage structure;
a conductive pad on an upper surface of the channel;
a first contact plug on the conductive pad;
a first bit line on the first contact plug;
a second contact plug on an upper surface of the second gate electrode; and
a second bit line on the second gate electrode, wherein:
the channel has a ring shape in a plan view, and
the second gate electrode is disposed inside the ring shape of the channel and is completely encircled by the channel in the plan view.