# US 11,444,096 B2 · Semiconductor device and manufacturing method of semiconductor device

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- Number: US 11,444,096 B2
- Document ID: US11444096B2
- Status: Granted
- Kind: B2
- Application number: 16/847,251
- Filed: 2020-04-13
- Published: 2021-05-20
- Granted: 2022-09-13
- Earliest claimed: 2019-11-15
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jin Ha Kim
- Web page: https://patentgrep.com/patent/US11444096B2

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/423: {Shielding layers}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a cell array including a source structure;
a peripheral circuit;
an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit; and
a decoupling structure located between the cell array and the interconnection structure and having an electrically floating state.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the decoupling structure has a mesh shape.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the decoupling structure comprises:
first conductive patterns; and
second conductive patterns crossing the first conductive patterns.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an interlayer insulating layer that is interposed between the cell array and the interconnection structure,
wherein the decoupling structure is formed in the interlayer insulating layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the decoupling structure is electrically separated from the cell array and the interconnection structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the interconnection structure includes wires that are coupled to a reference voltage generation circuit.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the decoupling structure prevents a coupling capacitor between the source structure and the wires.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the cell array further includes a bit line and a memory string, and
wherein the decoupling structure prevents a coupling capacitor between the source structure and the interconnection structure.

### Claim 9

A semiconductor device, comprising:
a source structure including a first surface and a second surface, the second surface being on an opposite side of the first surface;
a cell stacked structure that is located on the first surface of the source structure;
a first interconnection structure that is located on the second surface of the source structure; and
a decoupling structure located between the source structure and the first interconnection structure and having a mesh shape.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the decoupling structure has an electrically floating state.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first interconnection structure includes wires that are coupled to a reference voltage generation circuit.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the decoupling structure prevents a coupling capacitor between the source structure and the wires.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising a ground line applying a ground voltage to the decoupling structure.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the decoupling structure comprises:
first conductive patterns; and
second conductive patterns crossing the first conductive patterns.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the decoupling structure includes openings arranged in a first direction and a second direction, the second direction crossing the first direction.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a second interconnection structure that is located on the first surface of the source structure,
wherein the second interconnection structure includes a contact plug that is electrically coupled to the first interconnection structure through at least one of the openings.

### Claim 17 (depends on 9)

The semiconductor device of claim 9, further comprising a barrier layer contacting the decoupling structure.

### Claim 18 (depends on 9)

The semiconductor device of claim 9, wherein the decoupling structure includes a first surface facing the first interconnection structure and a second surface facing the source structure, and
the decoupling structure further comprises a first barrier layer contacting the first surface and a second barrier layer contacting the second surface.