# US 11,444,095 B2 · Semiconductor device with integrated memory devices and MOS devices and process of making the same

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- Number: US 11,444,095 B2
- Document ID: US11444095B2
- Status: Granted
- Kind: B2
- Application number: 17/229,848
- Filed: 2021-04-13
- Published: 2021-07-29
- Granted: 2022-09-13
- Earliest claimed: 2019-12-22
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Wang Xiang; Chia-Ching Hsu; Shen-De Wang; Weichang Liu
- Web page: https://patentgrep.com/patent/US11444095B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/01336: {on single crystalline silicon, e.g. chemical oxidation using a liquid}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

## Claims

### Claim 1

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, comprising:
a substrate with a first area and a second area;
multiple double-diffused metal-oxide-semiconductor (DMOS) devices on said first area, wherein said double-diffused metal-oxide-semiconductor (DMOS) device comprises a field oxide on said substrate, a first gate dielectric layer adjacent to said field oxide, and a first polysilicon gate on said field oxide and said first gate dielectric layer; and
multiple memory units on said second area, wherein said memory unit comprises an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on said oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of said second polysilicon gate of said memory unit in said second area and a top surface of said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) in said first area are on the same level.

### Claim 2 (depends on 1)

The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1, further comprising multiple complementary metal-oxide-semiconductor (CMOS) devices in said first area, wherein said complementary metal-oxide-semiconductor (CMOS) device comprises a second gate dielectric layer and a third polysilicon gate on said second gate dielectric layer, and a top surface of said third polysilicon gate of said complementary metal-oxide-semiconductor (CMOS) is on the same level as said top surface of said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) in said first area and said top surface of said second polysilicon gate of said memory unit in said second area.

### Claim 3 (depends on 2)

The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 2, wherein said first gate dielectric layers of said DMOS device is thicker than said second gate dielectric layers of said CMOS device.

### Claim 4 (depends on 1)

The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1, wherein said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) partly overlaps said field oxide at one sides.

### Claim 5 (depends on 1)

The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1, wherein said memory unit is silicon-oxide-nitride-oxide-silicon (SONOS) memory.