# US 11,444,094 B2 · Three-dimensional semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,094 B2 - Document ID: US11444094B2 - Status: Granted - Kind: B2 - Application number: 16/782,737 - Filed: 2020-02-05 - Published: 2020-09-24 - Granted: 2022-09-13 - Earliest claimed: 2019-03-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sejun Park; Jaeduk Lee; Jaehoon Jang; Jin-Kyu Kang; Seungwan Hong; Okcheon Hong - Web page: https://patentgrep.com/patent/US11444094B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 64/037: {comprising charge-trapping insulators} - H10D 64/516: {the thicknesses being non-uniform} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region. ## Claims ### Claim 1 A semiconductor memory device, comprising: a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and a vertical channel structure penetrating the stack structure, wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer, wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes, and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers, wherein the charge storage layer comprises a first portion and a remaining portion in the cell region, the first portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer, wherein the filling insulating layer is between the semiconductor pattern and the remaining portion of the charge storage layer of the cell region, and wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in a first direction parallel to the substrate. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein a bottom surface of the cell region and a bottom surface of the electrode adjacent to the cell region are at substantially same levels, respectively, and a top surface of the cell region and a top surface of the electrode adjacent to the cell region are at substantially same levels, respectively. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the remaining portion of the charge storage layer of the cell region is spaced apart from the tunnel insulating layer across the filling insulating layer. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein the tunnel insulating layer is between the charge storage layer and the semiconductor pattern. ### Claim 5 (depends on 1) The semiconductor memory device of claim 1, wherein the filling insulating layer of the cell separation region is between the charge storage layer and the tunnel insulating layer. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein each of the plurality of electrodes includes a protrusion part, which protrudes closer to the semiconductor pattern than an outer sidewall of the charge storage layer of the cell separation region. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein the protrusion part has a curved surface. ### Claim 8 (depends on 6) The semiconductor memory device of claim 6, wherein a maximum thickness of each of the plurality of protrusion parts is less than a maximum thickness of each of the plurality of electrodes, respectively. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein the filling insulating layer of the cell region has a first thickness in a first direction, and the filling insulating layer of the cell separation region has the second thickness in the first direction, the second thickness being greater than the first thickness. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, wherein the charge storage layer has a nonlinear shape between a pair of the plurality of electrodes adjacent to each other in a direction normal to the substrate. ### Claim 11 A semiconductor memory device, comprising: a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and a vertical channel structure penetrating the stack structure, wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer, wherein the filling insulating layer and the tunnel insulating layer are between the charge storage layer and the semiconductor pattern, wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers, wherein the filling insulating layer of the cell region has a first thickness in a first direction parallel to the substrate, wherein the filling insulating layer of the cell separation region has a second thickness in the first direction, the second thickness being greater than the first thickness, and wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in the first direction. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein a bottom surface of the cell region and a bottom surface of the electrode adjacent to the cell region are at substantially same levels, respectively, and a top surface of the cell region and a top surface of the electrode adjacent to the cell region are at substantially same levels, respectively. ### Claim 13 (depends on 11) The semiconductor memory device of claim 11, wherein the charge storage layer comprises a first portion and a remaining portion in the cell region; wherein the first portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer, and wherein the remaining portion of the charge storage layer of the cell region is spaced apart from the tunnel insulating layer across the filling insulating layer. ### Claim 14 (depends on 11) The semiconductor memory device of claim 11, wherein the filling insulating layer of the cell separation region is between the charge storage layer and the tunnel insulating layer. ### Claim 15 (depends on 11) The semiconductor memory device of claim 11, wherein the charge storage layer has a nonlinear shape between a pair of the plurality of electrodes adjacent to each other in a direction normal to the substrate. ### Claim 16 A semiconductor memory device, comprising: a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and a vertical channel structure penetrating the stack structure, wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer, wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers, wherein a bottom surface of the cell separation region and a bottom surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively, wherein a top surface of the cell separation region and a top surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively, wherein the filling insulating layer of the cell separation region extends from the bottom surface of the cell separation region to the top surface of the cell separation region, and wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in a first direction parallel to the substrate. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, wherein the cell region comprises a first cell region and a second cell region adjacent to the first cell region in a direction normal to the substrate, the cell separation region is between the first and second cell regions, and the filling insulating layer extends from the first cell region toward the second cell region. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, wherein the charge storage layer comprises a first portion and a remaining portion in the first cell region; wherein the first portion of the charge storage layer of the first cell region is in physical contact with the tunnel insulating layer, and wherein the filling insulating layer is between the semiconductor pattern and the remaining portion of the charge storage layer of the first cell region. ### Claim 19 (depends on 16) The semiconductor memory device of claim 16, wherein the filling insulating layer of the cell separation region is between the charge storage layer and the tunnel insulating layer. ### Claim 20 (depends on 16) The semiconductor memory device of claim 16, wherein the charge storage layer has a nonlinear shape between a pair of the plurality of electrodes adjacent to each other in a direction normal to the substrate.