# US 11,444,093 B2 · Memory arrays and methods of forming memory arrays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,093 B2 - Document ID: US11444093B2 - Status: Granted - Kind: B2 - Application number: 16/739,581 - Filed: 2020-01-10 - Published: 2021-07-15 - Granted: 2022-09-13 - Earliest claimed: 2020-01-10 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Chandra Tiwari - Web page: https://patentgrep.com/patent/US11444093B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 16/04: using variable threshold transistors, e.g. FAMOS - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. A horizontal pattern of operative memory-cell pillars extends through the insulative tiers and the conductive tiers in individual of the memory blocks. The operative memory-cell pillars have intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper of the insulative tiers and the conductive tiers. The at least one dummy structure is at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. The at least one dummy structure has intrinsic tensile mechanical stress. Other embodiments, including methods, are disclosed. ## Claims ### Claim 1 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks, the operative memory-cell pillars having intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper of the insulative tiers and the conductive tiers; the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern; the at least one dummy structure having intrinsic tensile mechanical stress; and the individual memory blocks comprise only one dummy structure in the at least one of the (a) and the (b). ### Claim 2 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks, the operative memory-cell pillars having intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper of the insulative tiers and the conductive tiers; the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern; the at least one dummy structure having intrinsic tensile mechanical stress; and the at least one dummy structure comprising the (a). ### Claim 3 (depends on 2) The memory array of claim 2 wherein the lateral edge is one of two opposing lateral edges, another of the at least one dummy structure being at the other of the two opposing lateral edges. ### Claim 4 (depends on 2) The memory array of claim 2 comprising the (a) and the (b). ### Claim 5 (depends on 4) The memory array of claim 4 wherein the lateral edge is one of two opposing lateral edges, another of the at least one dummy structure being at the other of the two opposing lateral edges. ### Claim 6 (depends on 2) The memory array of claim 2 wherein the at least one dummy structure comprises a plurality of insulative dummy pillars that are spaced longitudinally along the lateral edge of the horizontal pattern. ### Claim 7 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks, the operative memory-cell pillars having intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper of the insulative tiers and the conductive tiers; the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern; the at least one dummy structure having intrinsic tensile mechanical stress; the at least one dummy structure is a dummy pillar; the individual memory blocks comprise multiple of the dummy pillars in the at least one of the (a) and the (b); and the dummy pillars horizontally completely encircle the horizontal pattern. ### Claim 8 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks, the operative memory-cell pillars having intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper of the insulative tiers and the conductive tiers; the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern; the at least one dummy structure having intrinsic tensile mechanical stress; and the at least one dummy structure is a horizontally-elongated wall. ### Claim 9 (depends on 8) The memory array of claim 8 wherein the wall completely encircles the horizontal pattern. ### Claim 10 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks, the operative memory-cell pillars having intrinsic compressive mechanical stress; at least one dummy structure in the individual memory blocks extending through at least upper of the insulative tiers and the conductive tiers; the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern; the at least one dummy structure having intrinsic tensile mechanical stress; and the at least one dummy structure extends through uppermost of the insulative tiers and the conductive tiers and does not extend through a lowest of the insulative tiers and the conductive tiers, a void space being immediately-below the dummy structure. ### Claim 11 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks; and at least one dummy structure in the individual memory blocks, the at least one dummy structure extending through uppermost of the insulative tiers and the conductive tiers and not extending through a lowest of the insulative tiers and the conductive tiers, a void space being immediately-below the dummy structure. ### Claim 12 (depends on 11) The memory array of claim 11 wherein the operative memory-cell pillars have intrinsic compressive mechanical stress. ### Claim 13 (depends on 11) The memory array of claim 11 wherein the at least one dummy structure has intrinsic tensile mechanical stress. ### Claim 14 (depends on 11) The memory array of claim 11 wherein the operative memory-cell pillars are in a horizontal pattern, the at least one dummy structure being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. ### Claim 15 (depends on 11) The memory array of claim 11 wherein the at least one dummy structure is a dummy pillar. ### Claim 16 (depends on 11) The memory array of claim 11 wherein the at least one dummy structure is a horizontally-elongated wall. ### Claim 17 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, a horizontal pattern of operative memory-cell pillars extending through the insulative tiers and the conductive tiers in individual of the memory blocks; and a plurality of insulative dummy pillars in the individual memory blocks, the insulative dummy pillars extending through at least upper of the insulative tiers and the conductive tiers and at least predominately comprising AlOx; the insulative dummy pillars being spaced longitudinally along opposing lateral edges of the horizontal pattern longitudinally along the individual memory blocks. ### Claim 18 (depends on 17) The memory array of claim 17 wherein the insulative dummy pillars consist essentially of or consist of the AlOx. ### Claim 19 (depends on 17) The memory array of claim 17 wherein the insulative dummy pillars comprise conductive material. ### Claim 20 (depends on 17) The memory array of claim 17 wherein the insulative dummy pillars are devoid of conductive material. ### Claim 21 (depends on 17) The memory array of claim 17 wherein the insulative dummy pillars extend through all of the insulative tiers and the conductive tiers through which the operative memory-cell pillars extend. ### Claim 22 (depends on 17) The memory array of claim 17 wherein the insulative dummy pillars extend through uppermost of the insulative tiers and the conductive tiers and do not extend through a lowest of the insulative tiers and the conductive tiers. ### Claim 23 A method of forming a memory array comprising strings of memory cells, comprising: forming dummy structures in channel openings and in dummy-structure openings in a stack comprising vertically-alternating first tiers and second tiers; removing the dummy structures from the channel openings to leave the dummy structures in the dummy structure openings; and after the removing, forming operative memory-cell pillars in the channel openings. ### Claim 24 (depends on 23) The method of claim 23 wherein the removing is by etching that is conduced selectively relative to masking material that covers the dummy structures in the dummy-structure openings during said etching. ### Claim 25 (depends on 23) The method of claim 23 wherein the dummy structures in the channel openings and the dummy structures in dummy-structure openings are formed at the same time. ### Claim 26 (depends on 25) The method of claim 25 wherein the channel openings and the dummy structure openings are formed at the same time. ### Claim 27 (depends on 23) The method of claim 23 wherein the operative memory-cell pillars in the channel openings and the dummy structures in the dummy-structure openings are in a finished construction of the memory array, the operative memory-cell pillars having intrinsic compressive mechanical stress in the finished construction, the dummy structures having intrinsic tensile mechanical stress in the finished construction. ### Claim 28 (depends on 23) The method of claim 23 wherein the channel openings and the operative memory-cell pillars therein are formed in a horizontal pattern, the dummy structure openings and the dummy-structures therein being at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern.