# US 11,444,089 B2 · Gate-all-around field effect transistors in integrated circuits

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- Number: US 11,444,089 B2
- Document ID: US11444089B2
- Status: Granted
- Kind: B2
- Application number: 16/944,454
- Filed: 2020-07-31
- Published: 2021-07-01
- Granted: 2022-09-13
- Earliest claimed: 2019-12-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US11444089B2

## CPC

- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 14/3462: {Nanowires}
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a memory cell including a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region disposed lengthwise along a first direction and spaced from each other in said order along a second direction substantially perpendicular to the first direction,
wherein each of the first and the second p-type active regions includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction,
wherein each of the first and the second n-type active regions includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being less than the width W1, and
wherein each of the first p-type active region, the first n-type active region, the second n-type active region, and the second p-type active region extends along the first direction across a boundary of the memory cell.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein a ratio of the width W1 to the width W2 is about 1.1 to about 4.

### Claim 3 (depends on 1)

The IC structure of claim 1, wherein the memory cell further includes:
a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack oriented lengthwise along the second direction, the first and the second gate stacks being spaced from the third and the fourth gate stacks along the first direction,
wherein the first gate stack is disposed over the first p-type active region to provide a first n-type device,
wherein the second gate stack is disposed over the first n-type active region, the second n-type active region, and the second p-type active region to provide a first p-type device, a second p-type device, and a second n-type device, respectively,
wherein the third gate stack is disposed over the first p-type active region, the first n-type active region, and the second n-type active region to provide a third n-type device, a third p-type device, and a fourth p-type device, respectively, and
wherein the fourth gate stack is disposed over the second p-type active region to provide a fourth n-type device.

### Claim 4 (depends on 3)

The IC structure of claim 3, wherein each of the first and the fourth n-type devices is a pass-gate (PG) device, wherein each of the first and the fourth p-type devices is an isolation (IS) device, wherein each of the second and the third p-type devices is a pull-up (PU) device, and wherein each of the second and the third n-type devices is a pull-down (PD) device.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein each IS device includes a drain terminal, a source terminal, and a gate terminal electrically coupled to the source terminal or to the drain terminal.

### Claim 6 (depends on 1)

The IC structure of claim 1, wherein the memory cell is a first memory cell, the IC structure further comprising a second memory cell disposed adjacent to the first memory cell along the first direction, such that the first and the second p-type active regions and the first and the second n-type active regions extend along the first direction across both the first and the second memory cells.

### Claim 7 (depends on 1)

The IC structure of claim 1, wherein the memory cell further includes a first, a second, a third, a fourth, and a fifth dielectric structure disposed lengthwise along the first direction and spaced from each other in said order along the second direction,
wherein the first and the fifth dielectric structures are each disposed on a boundary of the memory cell,
wherein the second dielectric structure is disposed between the first p-type active region and the first n-type active region,
wherein the third dielectric structure is disposed between the first n-type active region and the second n-type active region, and
wherein the fourth dielectric structure is disposed between the second n-type active region and the second p-type active region.

### Claim 8 (depends on 7)

The IC structure of claim 7, wherein the first and the fifth dielectric structures are each defined by a width D1 along the second direction, wherein the second and the fourth dielectric structures are each defined by a width D2 along the second direction, and wherein the third dielectric structure is defined by a width D3 along the second direction, the widths D1, D2, and D3 being different.

### Claim 9 (depends on 8)

The IC structure of claim 8, wherein the width D1 is greater than the width D2, and wherein the width D2 is greater than the width D3.

### Claim 10

An integrated circuit (IC) structure, comprising:
a logic standard cell including an n-type active region and a p-type active region oriented lengthwise along a first direction and spaced from each other along a second direction substantially perpendicular to the first direction,
wherein the n-type active region includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and
wherein the p-type active region includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being greater than the width W2; and
a metal gate structure oriented lengthwise along the second direction, wherein the metal gate structure engages with the first plurality of vertically stacked channel layers to form a p-type device and with the second plurality of vertically stacked channel layers to form an n-type device.

### Claim 11 (depends on 10)

The IC structure of claim 10, wherein a ratio of the width W1 to the width W2 is about 1.1 to about 2.

### Claim 12 (depends on 10)

The IC structure of claim 10, wherein the logic standard cell is a first logic standard cell, the n-type active region is a first n-type active region, and the p-type active region is a first p-type active region, the IC structure further comprising a second logic standard cell disposed adjacent to the first logic standard cell along the first direction,
wherein the second standard logic cell includes a second n-type active region and a second p-type active region oriented along the first direction, and
wherein a boundary between the first logic standard cell and the second logic standard cell is defined by a dielectric gate structure oriented lengthwise along the second direction, such that the dielectric gate structure physically separates the first n-type active region and the first p-type active region from the second n-type active region and the second p-type active region, respectively.

### Claim 13 (depends on 12)

The IC structure of claim 12, wherein the first n-type active region and the second n-type active region have different lengths measured along the first direction, and wherein the first p-type active region and the second p-type active region have different lengths measured along the first direction.

### Claim 14 (depends on 10)

The IC structure of claim 10, wherein the logic standard cell is a first logic standard cell, the IC structure further comprising a second logic standard cell disposed adjacent to the first logic standard cell along the first direction, wherein the n-type active region and the p-type active region extend along the first direction across a boundary between the first logic standard cell and the second logic standard cell.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein the metal gate structure is a first metal gate structure, the p-type device is a first p-type device, and then-type device is a first n-type device, wherein the boundary is defined by a second metal gate structure, and wherein the second metal gate structure forms a second p-type isolation device with the n-type active region and a second n-type isolation device with the p-type active region.

### Claim 16 (depends on 10)

The IC structure of claim 10, wherein the logic standard cell further includes:
a first dielectric structure disposed at a first boundary of the logic standard cell and a second dielectric structure disposed at a second boundary of the logic standard cell and oriented lengthwise along the first direction, wherein each of the first and the second dielectric structures has a width D4 measured along the second direction, and
a third dielectric structure disposed between the n-type active region and the p-type active region and oriented lengthwise along the first direction, wherein the third dielectric structure has a width D5 measured along the second direction, the width D5 being less than or equal to the width D4.

### Claim 17 (depends on 10)

The IC structure of claim 10, wherein the n-type active region is a first n-type active region, and the p-type active region is a first p-type active region, the IC structure further comprising a memory cell that includes:
a second p-type active region, a second n-type active region, a third n-type active region, and a third p-type active region disposed lengthwise along the first direction and spaced from each other in said order along the second direction,
wherein each of the second and the third p-type active regions includes a third plurality of vertically stacked channel layers having a width W3 measured along the second direction,
wherein each of the second and the third n-type active regions includes a fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W4 being less than the width W3, and
wherein each of the second p-type active region, the second n-type active region, the third n-type active region, and the third p-type active region extends along the first direction across a boundary of the memory cell.

### Claim 18

An integrated circuit (IC) structure, comprising:
a memory cell that includes a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin disposed lengthwise along a first direction and spaced from each other in said order along a second direction substantially perpendicular to the first direction,
wherein each of the first and the second p-type fins includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction,
wherein each of the first and the second n-type fins includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being less than the width W1, and
wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin is continuous across a boundary of the memory cell;
a standard logic cell that includes a third n-type fin and a third p-type fin oriented lengthwise along the first direction and spaced from each other along the second direction,
wherein the third n-type fin includes a third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and
wherein the third p-type fin includes a fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being greater than or equal to the width W4; and
a plurality of metal gate structures disposed over the first, the second, and the third n-type fins to form p-type devices and over the first, the second, and the third p-type fins to form n-type devices.

### Claim 19 (depends on 18)

The IC structure of claim 18, wherein the standard logic cell further includes an isolation gate structure disposed at a boundary of the standard logic cell, the isolation gate structure being configured to form a p-type isolation device with the third n-type fin and an n-type isolation device with the third p-type fin.

### Claim 20 (depends on 18)

The IC structure of claim 18, wherein each of the third n-type fin and the third p-type fin is truncated at a boundary of the standard logic cell by a dielectric gate structure.