# US 11,444,088 B2 · Methods of forming integrated assemblies having conductive material along sidewall surfaces of semiconductor pillars

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- Number: US 11,444,088 B2
- Document ID: US11444088B2
- Status: Granted
- Kind: B2
- Application number: 17/070,759
- Filed: 2020-10-14
- Published: 2021-01-28
- Granted: 2022-09-13
- Earliest claimed: 2018-10-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hong Li; Ramaswamy Ishwar Venkatanarayanan; Sanh D. Tang; Erica L. Poelstra
- Web page: https://patentgrep.com/patent/US11444088B2

## CPC

- H10B 12/488: {Word lines}
- G11C 11/4023: {using field effect transistors}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/50: Bond wires
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

## Claims

### Claim 1

A method of forming an integrated assembly, comprising:
providing pillars of semiconductor material laterally spaced from one another by trenches; the pillars having upper segments, middle segments and lower segments; sidewall surfaces of the pillars defined by each segment and extending in the trenches;
forming liners along the sidewall surfaces of the pillars;
providing material over the liners and filling the trenches;
removing first sections of the liners to form gaps between the sidewall surfaces of the pillars and the material; second sections of the liners remaining under the gaps; and
forming conductive material within the gaps; the conductive material being configured as conductive lines; the conductive lines being along the middle segments of the pillars.

### Claim 2 (depends on 1)

The method of claim 1 wherein at least one trench has a greater width than the other trenches.

### Claim 3 (depends on 1)

The method of claim 1 further comprising, before the forming of the liners, forming an insulative layer against the sidewall surfaces of the pillars.

### Claim 4 (depends on 3)

The method of claim 3 wherein the removing of the first sections of the liners further comprises removing first sections of the insulative layer.

### Claim 5 (depends on 4)

The method of claim 4 further comprising replacing the first sections of the insulative layer with another insulative layer.

### Claim 6 (depends on 1)

The method of claim 1 further comprising recessing the material in the trenches before removing the first sections of the liners.

### Claim 7 (depends on 1)

The method of claim 1 wherein the semiconductor material is covered by a protective material.

### Claim 8 (depends on 7)

The method of claim 7 wherein, after forming the conductive material, removing the protective material to expose the upper segments of the pillars.

### Claim 9 (depends on 8)

The method of claim 8 wherein the upper segments comprise upper source/drain regions.

### Claim 10 (depends on 9)

The method of claim 9 further comprising coupling the upper source/drain regions to charge-storage devices.

### Claim 11 (depends on 1)

The method of claim 1 wherein the forming of the conductive material within the gaps does not completely fill the gaps.

### Claim 12 (depends on 11)

The method of claim 11 further comprising filling the gaps with more conductive material.

### Claim 13 (depends on 11)

The method of claim 11 further comprising filling the gaps with insulative material.

### Claim 14 (depends on 11)

The method of claim 11 further comprising filling another portion of the gaps with more conductive material leaving the gaps not completely filled.

### Claim 15 (depends on 11)

The method of claim 11 further comprising:
filling the gaps with insulative material; and
patterning the insulative material into spacers.

### Claim 16 (depends on 1)

The method of claim 1 wherein, after the forming of the conductive material, removing the material from within the trenches.

### Claim 17 (depends on 1)

The method of claim 1 wherein, after the forming of the conductive material, removing the second sections of the liners.