# US 11,444,087 B2 · Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same

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- Number: US 11,444,087 B2
- Document ID: US11444087B2
- Status: Granted
- Kind: B2
- Application number: 16/857,890
- Filed: 2020-04-24
- Published: 2021-10-28
- Granted: 2022-09-13
- Earliest claimed: 2020-04-24
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Kuo-Hui Su
- Web page: https://patentgrep.com/patent/US11444087B2

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device. The semiconductor memory device includes a substrate; an isolation member defining an active region having a first P-type ion concentration in the substrate; a gate structure disposed in the substrate; a first doped region positioned at a first side of the gate structure in the active region; a second doped region positioned at a second side of the gate structure in the active region; a bit line positioned on the first doped region; an air gap positioned adjacent to the bit line; a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug; and a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a substrate;
an isolation member defining an active region having a first P-type ion concentration in the substrate;
a gate structure disposed in the substrate;
a first doped region positioned at a first side of the gate structure in the active region;
a second doped region positioned at a second side of the gate structure in the active region;
a bit line positioned on the first doped region;
an air gap positioned adjacent to the bit line;
a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug;
a bit line spacer disposed between the air gap and the barrier layer; and
a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein an upper portion of the barrier layer is disposed between the protruding portion and the second silicide layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a top end of the second silicide layer is higher than a top end of the first silicide layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first silicide layer and the second silicide layer comprise polysilicon, the first silicide layer comprises tungsten, and the second silicide layer comprises titanium.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second silicide layer surrounds the first silicide layer.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the gate structure comprises: a gate dielectric layer conformally disposed on inner sidewalls of a gate trench; and a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the lower gate electrode includes polysilicon doped with an N-type ion, and the lower gate electrode is conformally disposed on the gate dielectric layer.

### Claim 8 (depends on 6)

The semiconductor memory device of claim 6, further comprising an intermediate gate electrode disposed between the lower gate electrode and the upper gate electrode, wherein the intermediate gate electrode includes a barrier metal, and the intermediate gate electrode is conformally disposed on the lower gate electrode.

### Claim 9 (depends on 6)

The semiconductor memory device of claim 6, wherein the upper gate electrode includes a metal, a metal alloy, or a metal compound, and the upper gate electrode fills the gate trench and has a rail-like shape.

### Claim 10 (depends on 6)

The semiconductor memory device of claim 6, further comprising a capping gate electrode covering an upper surface of the upper gate electrode, wherein the capping gate electrode includes a lower capping gate electrode and an upper capping gate electrode disposed on the lower capping gate electrode, and the lower capping gate electrode includes a barrier metal, and the upper capping gate electrode includes polysilicon doped with an N-type ion.