# US 11,444,085 B2 · Multi-layer thyristor random access memory with silicon-germanium bases

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- Number: US 11,444,085 B2
- Document ID: US11444085B2
- Status: Granted
- Kind: B2
- Application number: 17/229,695
- Filed: 2021-04-13
- Published: 2021-07-29
- Granted: 2022-09-13
- Earliest claimed: 2018-06-13
- Assignees: TC Lab, Inc.
- Applicants: TC Lab, Inc.
- Inventors: Harry Luan
- Web page: https://patentgrep.com/patent/US11444085B2

## CPC

- G11C 11/39: using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/01: {Manufacture or treatment}
- H10B 12/10: DRAM devices comprising bipolar components
- H10D 18/031: {of lateral or planar thyristors}
- H10D 18/251: {Lateral thyristors}
- H10D 62/192: {Base regions of thyristors}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

## Claims

### Claim 1

A semiconductor fabrication process comprising:
depositing alternating layers of insulating material and first material on a semiconductor substrate;
etching trenches through the alternating layers;
removing the first material by laterally etching it from between the layers of insulating material to form cavities between the layers of insulating material;
introducing a silicon containing gas and first conductivity type impurity into the process to thereby form one of a cathode or an anode for semiconductor devices in the cavities;
introducing semiconductor material having an energy bandgap less than of silicon together with first and opposite conductivity type impurities to thereby form interior regions between the cathode and anode for the semiconductor devices;
introducing a silicon containing gas and opposite conductivity type impurity into the process to thereby form the other of a cathode or an anode for the semiconductor devices in the cavities; and
providing electrical connections to the semiconductor devices in the cavities.

### Claim 2 (depends on 1)

A semiconductor fabrication process as in claim 1 wherein the step of introducing semiconductor material having an energy bandgap less than of silicon together with first and opposite conductivity type impurities further comprises:
introducing silicon-germanium into the process, together with opposite conductivity type impurity to thereby form a first interior region for the semiconductor devices in the cavities; and
introducing silicon-germanium into the process, together with first conductivity type impurity to thereby form a second interior region for the semiconductor devices in the cavities.

### Claim 3 (depends on 2)

A semiconductor fabrication process as in claim 2 wherein the step of etching trenches further comprises:
etching first trenches in a first direction;
forming single crystal semiconductor material on walls of the first trenches;
etching pairs of the alternating layers of insulating material and first material to form a staircase structure;
etching second trenches in a second direction orthogonal to the first direction; and then
removing the first material by laterally etching it.

### Claim 4 (depends on 2)

A semiconductor fabrication process as in claim 2 wherein a single crystal semiconductor material provides a substrate for formation of single crystal semiconductor material in the cavities.

### Claim 5 (depends on 2)

A process as in claim 2 wherein the first and opposite conductivity type impurity interior regions preferably have constant germanium compositions of 2-30 percent mole fraction.

### Claim 6 (depends on 2)

A process as in claim 2 wherein germanium compositions in the first and opposite conductivity type impurity interior regions vary across the interior regions.

### Claim 7 (depends on 6)

A process as in claim 6 wherein the germanium composition is graded such that germanium mole fraction is lower near a junction between the first and opposite conductivity type impurity interior regions and higher towards both anode and the cathode junctions.

### Claim 8 (depends on 7)

A process as in claim 7 wherein the germanium composition is linearly graded.

### Claim 9 (depends on 6)

A process as in claim 6 wherein the germanium composition is graded such that germanium mole fraction is higher near a junction between the first and opposite conductivity type impurity interior regions and higher towards both anode and the cathode junctions.

### Claim 10 (depends on 9)

A process as in claim 9 wherein the germanium composition is linearly graded.