# US 11,444,083 B2 · Fabrication of fin field effect transistors utilizing different fin channel materials while maintaining consistent fin widths > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,083 B2 - Document ID: US11444083B2 - Status: Granted - Kind: B2 - Application number: 16/866,150 - Filed: 2020-05-04 - Published: 2020-08-20 - Granted: 2022-09-13 - Earliest claimed: 2017-02-27 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kangguo Cheng; Juntao Li; Peng Xu - Web page: https://patentgrep.com/patent/US11444083B2 ## CPC - H10D 84/853: {comprising FinFETs} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins} - H10D 30/751: {having composition variations in the channel regions} - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 84/0158: {the components including FinFETs} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/834: {comprising FinFETs} - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar. ## Claims ### Claim 1 A semiconductor device with vertical fins on a substrate, comprising: one or more vertical fins formed on a first region of a substrate, wherein each of the one or more vertical fins formed on the first region of the substrate includes a fin core and a flared fin section made of the same material as the substrate; one or more vertical fins formed on a second region of the substrate, where the second region of the substrate is adjacent to the first region of the substrate, and wherein each of the one or more vertical fins formed on the second region of the substrate includes a pillar core and. a flared pillar section made of a different material than the one or more vertical fins formed on the first region of the substrate, wherein each of the one or more pillar cores includes germanium; and a filler layer on the substrate, wherein a top surface of the filler layer intersects the flared fin section and the flared pillar section, and wherein the flared pillar sections below the top surface of the filler layer have a germanium concentration gradient. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein each of the one or more pillar cores have a germanium concentration in a range of about 20 at. % to about 50 at. %. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein each of the one or more fin cores and each of the one or more pillar cores have essentially the same width that is less than the width of a lower fin section below each of the fin cores. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the flared pillar sections have a width in a range of about 15 nanometers (nm) to about 20 nm at an interface with an underlying substrate pillar, and the fin cores and pillar cores each have a width in a range of about 5 nm to about 10 nm. ### Claim 5 (depends on 4) The semiconductor device of claim 4, further comprising, a gate structure on the one or more vertical fins formed on the first region of a substrate, and a gate structure on the one or more vertical fins formed on the second region of the substrate. ### Claim 6 (depends on 5) The semiconductor device of claim 5, further comprising a first punch-through stop (PTS) below each of the pillar cores. ### Claim 7 (depends on 6) The semiconductor device of claim 6, further comprising a second punch-through stop (PTS) below each of the fin cores. ### Claim 8 (depends on 7) The semiconductor device of claim 7, further comprising an isolation trench formed through the gate structure between fin cores on the first region of the substrate and the pillar cores on the second region of the substrate. ### Claim 9 A semiconductor device with vertical fins on a substrate, comprising: one or more vertical fins formed on a first region of a substrate, wherein each of the one or more vertical fins formed on the first region of the substrate includes a fin core, a lower fin section, and a flared fin section between the fin core and the lower fin section, wherein the one or more vertical fins formed on the first region of the substrate are made of the same material as the substrate; one or more vertical fins formed on a second region of the substrate, where the second region of the substrate is adjacent to the first region of the substrate, and wherein each of the one or more vertical fins formed on the second region of the substrate includes a pillar core, a substrate pillar, and a flared pillar section between the pillar core and the substrate pillar, wherein the one or more vertical fins formed on the second region of the substrate include different material than the one or more vertical fins formed on the first region of the substrate, and the pillar cores have essentially the same width as the fin cores; and a filler layer on the substrate, wherein a top surface of the filler layer intersects the flared fin section, wherein the flared pillar sections below the top surface of the filler layer have a germanium concentration gradient. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the fin core is silicon, the pillar core is silicon germanium, and the substrate pillar is silicon. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the germanium concentration of the pillar core is in the range of about 10 at. % to about 85 at. %. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the substrate is single crystal silicon. ### Claim 13 (depends on 9) The semiconductor device of claim 9, further comprising a high-K gate dielectric layer directly on the exposed surfaces of the fin cores, pillar cores, and top surface of the filler layer. ### Claim 14 A semiconductor device with vertical fins on a substrate, comprising: one or more vertical fins formed on a first region of a substrate, wherein each of the one or more vertical fins formed on a first region of a substrate includes a fin core, a lower fin section, and a flared fin section between the fin core and the lower fin section, wherein the one or more vertical fins formed on the first region of the substrate are made of the same material as the substrate; one or more vertical fins formed on a second region of the substrate, where the second region of the substrate is adjacent to the first region of the substrate, and wherein each of the one or more vertical fins formed on the second region of the substrate includes a pillar core, a substrate pillar, and a flared pillar section between the pillar core and the substrate pillar, wherein the one or more vertical fins formed on the second region of the substrate include a different material than the one or more vertical fins formed on the first region of the substrate, wherein the one or more fin cores and the one or more pillar cores have essentially the same width; a filler layer on the substrate, wherein a top surface of the filler layer intersects the flared fin section; a first punch-through stop (PTS) below each of the pillar cores; and. a second punch-through stop (PTS) below each of the fin cores. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein different dopants are in the flared fin sections and the lower fin sections for the first punch-through stop than in the flared pillar sections and the substrate pillars for the second punch-through stop. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein each of the fin cores and each of the pillar cores have a width that is less than the width, W1, of a lower fin section below each of the fin cores. ### Claim 17 (depends on 16) The semiconductor device of claim 16, further comprising, a first gate structure on the one or more fin cores on the first region of a substrate, and a second gate structure on the one or more pillar cores on the second region of the substrate, wherein each of the one or more fin cores are silicon, and each of the one or more pillar cores are silicon-germanium. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the one or more vertical fins and gate structure on the first region of the substrate form a n-type field effect transistor (NFET), the one or more vertical fins and gate structure on the second region of the substrate form a p-type field effect transistor (PFET), and the NFET and PFET are electrically coupled to form a complementary metal oxide semiconductor (CMOS) device.