# US 11,444,082 B2 · Semiconductor apparatus having stacked gates and method of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,082 B2 - Document ID: US11444082B2 - Status: Granted - Kind: B2 - Application number: 17/039,307 - Filed: 2020-09-30 - Published: 2021-01-28 - Granted: 2022-09-13 - Earliest claimed: 2017-12-04 - Assignees: Tokyo Electron Limited - Applicants: Tokyo Electron Limited - Inventors: Jeffrey Smith; Anton J. deVilliers; Kandabara N. Tapily; Subhadeep Kal; Gerrit J. Leusink - Web page: https://patentgrep.com/patent/US11444082B2 ## CPC - H10D 84/85: Complementary IGFETs, e.g. CMOS - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0179: {the gate conductors having different shapes or dimensions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 88/00: Three-dimensional [3D] integrated devices - H10D 88/01: {Manufacture or treatment} - H10P 14/3462: {Nanowires} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed. ## Claims ### Claim 1 A method for forming a semiconductor apparatus, the method comprising: forming a first field-effect transistor (FET) that comprises a first channel and a first gate disposed all around the first channel on a substrate of the semiconductor apparatus, the first channel configured to have a first current flow path parallel to a main surface of the substrate; forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the main surface of the substrate and comprises a second channel and a second gate disposed all around the second channel, the second channel configured to have a second current flow path parallel to the main surface of the substrate, the first channel and the second channel separated and conductively isolated from each other; forming a first routing track and a second routing track that is electrically isolated from the first routing track, each of the first and second routing tracks being provided on a routing plane stacked on the second FET along the direction; forming a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track; and forming a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the second FET comprises stacking the second gate directly above the first gate along the direction substantially perpendicular to the main surface of the substrate. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the first routing track and the second routing track comprises forming the first routing track and the second routing track above the second gate along the direction substantially perpendicular to the main surface of the substrate. ### Claim 4 (depends on 1) The method of claim 1, wherein forming the first conductive trace comprises forming the first conductive trace that bypasses the second gate and the second FET. ### Claim 5 (depends on 1) The method of claim 1, further comprising: forming a third FET that includes a third gate on the substrate; forming a fourth FET that is stacked on the third FET along the direction substantially perpendicular to the main surface of the substrate and includes a fourth gate; forming a third conductive trace configured to conductively couple the third gate of the third FET to the second routing track; and forming a fourth conductive trace configured to conductively couple the fourth gate of the fourth FET to the first routing track. ### Claim 6 (depends on 5) The method of claim 5, wherein forming the fourth FET comprises stacking the fourth gate on the third gate along the direction. ### Claim 7 (depends on 5) The method of claim 5, wherein forming the third conductive trace comprises forming the third conductive trace that bypasses the fourth gate and the fourth FET. ### Claim 8 (depends on 5) The method of claim 5, wherein the second gate is stacked on the first gate and the fourth gate is stacked on the third gate, the first and second routing tracks are provided on one or more routing planes above the first, second, third, and fourth gates along the direction, the first conductive trace and the second conductive trace are spatially separated, the first conductive trace bypasses the second gate and the second FET, and the second conductive trace bypasses the first gate and the first FET, the third and fourth conductive trace are spatially separated, the third conductive trace bypasses the fourth gate and the fourth FET, and the fourth conductive trace bypasses the third gate and the third FET, the first and fourth gates are conductively coupled to the first routing track via the first and fourth conductive traces, respectively, and the second and third gates are conductively coupled to the second routing track via the second and third conductive traces, respectively. ### Claim 9 (depends on 8) The method of claim 8, wherein a second gate area that is a gate area being a maximum cross-sectional area of the gate intersecting with a plane substantially perpendicular to the direction substantially perpendicular to the main surface of the substrate, is equal to or larger than a first gate area; a fourth gate area is equal to or larger than a third gate area; forming the second FET includes staggering the second gate above the first gate; and forming the fourth FET includes staggering the fourth gate above the third gate. ### Claim 10 (depends on 8) The method of claim 8, wherein a second gate area is less than a first gate area; a fourth gate area is less than a third gate area; forming the second FET includes staggering the second gate above the first gate; and forming the fourth FET includes staggering the fourth gate above the third gate. ### Claim 11 (depends on 1) The method of claim 1, wherein at least one of the first and the second gates includes a conductive material having an anisotropic etching property. ### Claim 12 (depends on 1) The method of claim 1, wherein forming the first FET includes forming one of a n-type FET and a p-type FET to be the first FET; and forming the second FET includes forming another one of the n-type FET and the p-type FET to be the second FET, the first FET and the second FET being complementary FETs. ### Claim 13 (depends on 1) The method of claim 1, wherein the first channel comprises a first set of semiconductor bars stacked along the direction, and the second channel comprises a second set of semiconductor bars stacked along the direction. ### Claim 14 (depends on 13) The method of claim 13, wherein at least one of the first gate and the second gate includes a first structure covering at least one of the first set of semiconductor bars and the second set of semiconductor bars, a second structure covering the first structure, and a third structure covering the second structure. ### Claim 15 (depends on 14) The method of claim 14, wherein the first structure includes a layer having high dielectric constant (high-k layer) and a barrier layer that prevents diffusion between the high-k layer and the second structure, the second structure includes a work-function layer that adjusts a work-function of the respective gate and a blocking layer that prevents diffusion between the work-function layer and the third structure, and the third structure includes one or more conductive materials. ### Claim 16 (depends on 13) The method of claim 13, further comprising stacking the second set of semiconductor bars over the first set of semiconductors bars along the direction. ### Claim 17 (depends on 1) The method of claim 1, wherein at least one of the first gate and the second gate includes a transition metal. ### Claim 18 (depends on 17) The method of claim 17, wherein the transition metal is Ruthenium. ### Claim 19 (depends on 1) The method of claim 1, further comprising: forming a dielectric layer that includes one or more dielectric materials between the first gate and the second gate, the dielectric layer separating and conductively isolating the first gate and the second gate. ### Claim 20 A method for forming a semiconductor apparatus, comprising: forming a first field-effect transistor (FET) including a first gate and a first channel on a substrate of the semiconductor apparatus; forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate and a second channel, the first channel and the second channel being separated and conductively isolated by a dielectric layer, and the first gate and the second gate being separated and conductively isolated by the dielectric layer; forming a first routing track and a second routing track electrically isolated from the first routing track, each of the first and second routing tracks being provided on a routing plane stacked on the second FET along the direction; forming a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, the first conductive trace bypassing the second gate and the second FET; and forming a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.