# US 11,444,081 B2 · Integrated circuit (IC) device

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- Number: US 11,444,081 B2
- Document ID: US11444081B2
- Status: Granted
- Kind: B2
- Application number: 17/150,712
- Filed: 2021-01-15
- Published: 2021-08-05
- Granted: 2022-09-13
- Earliest claimed: 2018-09-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Myung-gil Kang; Beom-jin Park; Geum-jong Bae; Dong-won Kim; Jung-gil Yang
- Web page: https://patentgrep.com/patent/US11444081B2

## CPC

- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

## Claims

### Claim 1

An integrated circuit device comprising:
a fin-type active area protruding from a substrate and extending in a first horizontal direction;
a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween;
a second nanosheet disposed above the first nanosheet with a second separation space therebetween;
a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, a portion of the gate line being disposed in the second separation space; and
a bottom insulation structure disposed in the first separation space,
wherein a thickness of the first nanosheet in a vertical direction is less than a thickness of the second nanosheet in the vertical direction.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the bottom insulation structure has a bottom surface contacting the upper surface of the fin-type active area, and a top surface contacting the first nanosheet.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein a first height of the first separation space in the vertical direction is less than a second height of the second separation space in the vertical direction.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a first insulation spacer interposed between the upper surface of the fin-type active area and the first nanosheet; and
a second insulation spacer interposed between the first nanosheet and the second nanosheet, the second insulation spacer having a height greater than a height of the first insulation spacer in the vertical direction.

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a pair of insulation spacers interposed between the upper surface of the fin-type active area and the first nanosheet,
wherein the pair of insulation spacers are spaced apart from each other with the bottom insulation structure interposed between the pair of insulation spacers.

### Claim 6 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a gate dielectric layer covering the first nanosheet and the second nanosheet,
wherein a thickness of the bottom insulation structure is greater than a thickness of the gate dielectric layer.

### Claim 7 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a pair of source/drain regions disposed at both sides of the gate line on the fin-type active area,
wherein each of the pair of source/drain regions contacts the first nanosheet and the second nanosheet, and
wherein the bottom insulation structure is spaced apart from the pair of source/drain regions in the first horizontal direction.

### Claim 8 (depends on 1)

The integrated circuit device of claim 1, wherein a width of the bottom insulation structure in the first horizontal direction is less than a width of each of the first nanosheet and the second nanosheet in the first horizontal direction.

### Claim 9 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a gate dielectric layer covering the first nanosheet and the second nanosheet,
wherein the gate dielectric layer is integrally connected to the bottom insulation structure.

### Claim 10 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a source/drain region disposed on the fin-type active area and covering respective sidewalls of the first nanosheet and the second nanosheet; and
an insulation spacer interposed between the bottom insulation structure and the source/drain region,
wherein a height of the insulation spacer in the vertical direction is less than a height of the second separation space in the vertical direction.

### Claim 11

An integrated circuit device comprising:
a fin-type active area protruding from a substrate and extending in a first horizontal direction;
a pair of source/drain regions disposed on the fin-type active area;
a nanosheet stack structure facing an upper surface of the fin-type active area with a first separation space between the nanosheet stack structure and the upper surface, the nanosheet stack structure comprising a plurality of nanosheets of which widths in the first horizontal direction are defined by the pair of source/drain regions;
a gate line extending on the fin-type active area in a second horizontal direction intersecting the first horizontal direction and having a sub-gate portion disposed within a second separation space between the plurality of nanosheets;
a gate dielectric layer interposed between the plurality of nanosheets and the gate line; and
a bottom insulation structure filling the first separation space,
wherein a vertical thickness of a first nanosheet closest to the fin-type active area from among the plurality of nanosheets is less than a vertical thickness of a second nanosheet from among the plurality of nanosheets, the second nanosheet disposed above the first nanosheet.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, wherein the bottom insulation structure has a bottom surface contacting the upper surface of the fin-type active area, and a top surface contacting the first nanosheet.

### Claim 13 (depends on 11)

The integrated circuit device of claim 11, further comprising:
a first insulation spacer interposed between the upper surface of the fin-type active area and the first nanosheet; and
at least one second insulation spacer interposed between the plurality of nanosheets,
wherein the first insulation spacer has a height less than a height of the at least one second insulation spacer.

### Claim 14 (depends on 11)

The integrated circuit device of claim 11, further comprising:
a pair of insulation spacers interposed between the upper surface of the fin-type active area and the first nanosheet,
wherein the pair of insulation spacers are spaced apart from each other with the bottom insulation structure interposed between the pair of insulation spacers.

### Claim 15 (depends on 11)

The integrated circuit device of claim 11, wherein a thickness of the bottom insulation structure is greater than a thickness of the gate dielectric layer.

### Claim 16 (depends on 11)

The integrated circuit device of claim 11, further comprising:
a pair of insulation spacers interposed between the upper surface of the fin-type active area and the first nanosheet,
wherein the bottom insulation structure is spaced apart from the pair of source/drain regions in the first horizontal direction with the pair of insulation spacers therebetween.

### Claim 17 (depends on 11)

The integrated circuit device of claim 11, wherein a width of the bottom insulation structure in the first horizontal direction is less than a width of each of the first nanosheet and the second nanosheet in the first horizontal direction.

### Claim 18

An integrated circuit device comprising:
a fin-type active area extending on a substrate in a first horizontal direction;
a source/drain region disposed on the fin-type active area;
a nanosheet stack structure disposed on the fin-type active area, the nanosheet stack structure comprising a first nanosheet closest to the fin-type active area and a second nanosheet disposed above the first nanosheet;
a gate line covering the nanosheet stack structure on the fin-type active area, and extending in a second horizontal direction intersecting the first horizontal direction;
a gate dielectric layer disposed between the nanosheet stack structure and the gate line; and
a bottom insulation structure interposed between the fin-type active area and the first nanosheet, and integrally connected to the gate dielectric layer,
wherein a thickness of the first nanosheet in a vertical direction is less than a thickness of the second nanosheet in the vertical direction.

### Claim 19 (depends on 18)

The integrated circuit device of claim 18, wherein the bottom insulation structure has a bottom surface contacting the fin-type active area, and a top surface contacting the first nanosheet.

### Claim 20 (depends on 18)

The integrated circuit device of claim 18, wherein the bottom insulation structure comprises a first insulation portion and a second insulation portion,
wherein the first insulation portion fills a space between the fin-type active area and the first nanosheet, and the second insulation portion extends from the first insulation portion in the second horizontal direction and is interposed between the fin-type active area and the gate line.