# US 11,444,080 B2 · Semiconductor structure cutting process and structures formed thereby

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- Number: US 11,444,080 B2
- Document ID: US11444080B2
- Status: Granted
- Kind: B2
- Application number: 17/085,121
- Filed: 2020-10-30
- Published: 2021-02-18
- Granted: 2022-09-13
- Earliest claimed: 2017-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chang Hung; Chia-Jen Chen; Ming-Ching Chang; Shu-Yuan Ku; Yi-Hsuan Hsiao; I-Wei Yang
- Web page: https://patentgrep.com/patent/US11444080B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 64/679: {comprising air gaps}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/40: of conductive or resistive materials
- H10P 50/267: {using plasmas}
- H10P 50/283: {by chemical means}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 52/403: {of conductive or resistive materials}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

## Claims

### Claim 1

A structure comprising:
a first fin protruding from a substrate;
a second fin protruding from the substrate;
a first gate structure extending over the first fin;
a second gate structure extending over the second fin, the first gate structure and the second gate structure being longitudinally aligned;
a first gate spacer along a sidewall of the first gate structure;
a second gate spacer along a sidewall of the second gate structure; and
a gate cut-fill structure interposed between the first gate structure and the second gate structure, the gate cut-fill structure being interposed between the first gate spacer and the second gate spacer, wherein a first width of the gate cut-fill structure between the first gate spacer and the second gate spacer is less than a second width of the gate cut-fill structure between the first gate structure and the second gate structure.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising:
a first source/drain region over the first fin and adjacent the first gate structure; and
a second source/drain region over the second fin and adjacent the second gate structure, wherein the gate cut-fill structure is interposed between the first source/drain region and the second source/drain region, wherein a third width of the gate cut-fill structure between the first source/drain region and the second source/drain region is greater than the first width.

### Claim 3 (depends on 2)

The structure of claim 2, wherein the first source/drain region and the second source/drain region are epitaxial regions.

### Claim 4 (depends on 3)

The structure of claim 3, wherein a distance between the first source/drain region and the gate cut-fill structure is in a range from 5 nm to 15 nm.

### Claim 5 (depends on 4)

The structure of claim 4, wherein a distance between the second source/drain region and the gate cut-fill structure is in a range from 5 nm to 15 nm.

### Claim 6 (depends on 1)

The structure of claim 1 further comprising:
isolation regions interposed between the first fin and the second fin, wherein the first fin and the second fin protrude above the isolation regions, wherein the gate cut-fill structure extends to the isolation regions.

### Claim 7 (depends on 6)

The structure of claim 6, wherein the gate cut-fill structure comprises:
a dielectric material layer along sidewalls of the first gate structure and the second gate structure; and
a void in the dielectric material layer, wherein the dielectric material layer completely separates the void from the isolation regions.

### Claim 8

A structure comprising:
a first gate structure and a second gate structure extending along a first line;
a third gate structure and a fourth gate structure extending along a second line;
a first gate spacer along a sidewall of the first gate structure;
a second gate spacer along a sidewall of the second gate structure;
a third gate spacer along a sidewall of the third gate structure;
a fourth gate spacer along a sidewall of the fourth gate structure;
a first source/drain region interposed between the first gate structure and the third gate structure;
a second source/drain region interposed between the second gate structure and the fourth gate structure;
a first dielectric layer over the first source/drain region and the second source/drain region; and
a gate cut-fill structure interposed between the first gate structure and the second gate structure, the gate cut-fill structure being interposed between the first gate spacer and the second gate spacer, the gate cut-fill structure being interposed between the third gate spacer and the fourth gate spacer, the gate cut-fill structure extending through the first dielectric layer interposed between the first source/drain region and the second source/drain region, wherein a width of the gate cut-fill structure extending through the first dielectric layer is less than a width of the gate cut-fill structure interposed between the first gate structure and the second gate structure, wherein the width of the gate cut-fill structure extending through the first dielectric layer is less than a width of the gate cut-fill structure interposed between the third gate structure and the fourth gate structure.

### Claim 9 (depends on 8)

The structure of claim 8, wherein the first gate structure and the third gate structure extends over a first fin, and wherein the second gate structure and the fourth gate structure extends over a second fin.

### Claim 10 (depends on 8)

The structure of claim 8, wherein:
a width of the gate cut-fill structure interposed between the first gate spacer and the second gate spacer is less than the width of the gate cut-fill structure extending through the first dielectric layer between the first source/drain region and the second source/drain region,
the width of the gate cut-fill structure interposed between the first gate spacer and the second gate spacer is less than the width of the gate cut-fill structure interposed between the first gate structure and the second gate structure, and
the width of the gate cut-fill structure interposed between the first gate spacer and the second gate spacer is less than the width of the gate cut-fill structure interposed between the third gate structure and the fourth gate structure.

### Claim 11 (depends on 8)

The structure of claim 8 further comprising a second dielectric layer extending over the first dielectric layer and over the gate cut-fill structure.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the gate cut-fill structure comprises:
a third dielectric layer along sidewalls of the first gate structure, the second gate structure, the third gate structure and the fourth gate structure; and
a first void interposed between the first gate structure and the second gate structure, wherein the second dielectric layer forms an upper surface of the first void.

### Claim 13 (depends on 12)

The structure of claim 12, wherein the gate cut-fill structure further comprises:
a second void interposed between the third gate structure and the fourth gate structure, wherein the first dielectric layer separates the first void and the second void.

### Claim 14 (depends on 12)

The structure of claim 12, wherein the first void extends continuously between the first source/drain region and the second source/drain region, wherein the first void extends continuously between the third gate structure and the fourth gate structure.

### Claim 15

A structure comprising:
a first fin protruding from a substrate;
a second fin protruding from the substrate;
a first gate electrode extending over the first fin;
a second gate electrode extending over the second fin, the first gate electrode and the second gate electrode being longitudinally aligned;
a first gate spacer along a first sidewall of the first gate electrode and along a first sidewall of the second gate electrode;
a second gate spacer along a second sidewall of the first gate electrode and along a second sidewall of the second gate electrode; and
a gate cut-fill structure interposed between the first gate electrode and the second gate electrode, the gate cut-fill structure extending over an upper surface of the first gate spacer and the second gate spacer.

### Claim 16 (depends on 15)

The structure of claim 15 further comprising a gate dielectric interposed between the first gate electrode and the first fin and interposed between the second gate electrode and the second fin, the gate dielectric extending continuously between the first gate electrode to the second gate electrode.

### Claim 17 (depends on 16)

The structure of claim 16, wherein an upper surface of the first gate spacer below the gate cut-fill structure is higher than an upper surface of the gate dielectric below the gate cut-fill structure.

### Claim 18 (depends on 15)

The structure of claim 15, wherein the gate cut-fill structure is interposed between the first gate spacer and the second gate spacer.

### Claim 19 (depends on 15)

The structure of claim 15, wherein a first width of the gate cut-fill structure directly over the first gate spacer is less than a second width of the gate cut-fill structure between the first gate electrode and the second gate electrode.

### Claim 20 (depends on 15)

The structure of claim 15, wherein the gate cut-fill structure directly contacts opposite sidewalls of the first gate spacer.