# US 11,444,075 B2 · Isolation structure for IC with epi regions sharing the same tank

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- Number: US 11,444,075 B2
- Document ID: US11444075B2
- Status: Granted
- Kind: B2
- Application number: 16/666,563
- Filed: 2019-10-29
- Published: 2020-02-27
- Granted: 2022-09-13
- Earliest claimed: 2014-05-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Henry Litzmann Edwards; Akram A. Salman; Binghua Hu
- Web page: https://patentgrep.com/patent/US11444075B2

## CPC

- H10D 89/711: {using bipolar transistors as protective elements}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 84/0112: {Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.

## Claims

### Claim 1

An integrated circuit, comprising:
a p-type semiconductor substrate;
a plurality of spaced-apart deep trench (DT) structures;
a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures and merging with at least one neighboring DEEPN diffusion region surrounding at least one neighboring DT structure; and
an n-type buried layer (NBL) within the semiconductor substrate, wherein each DEEPN diffusion region extends from a surface of the semiconductor substrate through a p-type semiconductor layer to the NBL.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein each DT structure extends from the surface through the NBL.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the DT structures each include a dielectric sidewall and a polysilicon core.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the polysilicon core connects to the p-type substrate below the NBL.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the DT structures form a linear array.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising a DT ring surrounding an enclosed area of the semiconductor substrate, wherein the plurality of DEEPN diffusion regions form a continuous DEEPN region connecting to first and second locations on the DT ring.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the plurality of DEEPN diffusion regions divide the enclosed area into first and second sub-areas, the first sub-area including a first electronic device and the second sub-area including a second electronic device.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the first and second electronic devices are electrostatic discharge (ESD) devices.

### Claim 9 (depends on 7)

The integrated circuit of claim 7, wherein the NBL provides a current path between the first and second electronic devices.

### Claim 10

An integrated circuit, comprising:
a p-type semiconductor substrate;
a plurality of spaced-apart deep trench (DT) structures;
a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures and merging with at least one neighboring DEEPN diffusion region surrounding at least one neighboring DT structure; and
an n-type buried layer (NBL) within the semiconductor substrate, wherein each DT structure extends from a surface of the semiconductor substrate through the NBL.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the DT structures each include a dielectric sidewall and a polysilicon core.

### Claim 12 (depends on 10)

The integrated circuit of claim 10, wherein polysilicon cores within the DT structures connect to the p-type substrate below the NBL.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, further comprising a DT ring surrounding an enclosed area of the semiconductor substrate, wherein the plurality of DEEPN diffusion regions form a continuous DEEPN region connecting to first and second locations on the DT ring.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the plurality of DEEPN diffusion regions divide the enclosed area into first and second sub-areas, the first sub-area including a first electronic device and the second sub-area including a second electronic device.

### Claim 15

An integrated circuit, comprising:
a p-type semiconductor substrate;
a plurality of spaced-apart deep trench (DT) structures;
a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures and merging with at least one neighboring DEEPN diffusion region surrounding at least one neighboring DT structure; and
a DT ring surrounding an enclosed area of the semiconductor substrate, wherein the plurality of DEEPN diffusion regions form a continuous DEEPN region connecting to first and second locations on the DT ring.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, further comprising an n-type buried layer (NBL) within the semiconductor substrate, wherein each DEEPN diffusion region extends from a surface of the semiconductor substrate through a p-type semiconductor layer to the NBL.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the continuous DEEPN region is located between first and second electronic devices, and the NBL provides a current path between the first and second electronic devices.

### Claim 18 (depends on 15)

The integrated circuit of claim 15, further comprising an n-type buried layer (NBL) within the semiconductor substrate, wherein each DT structure extends from a surface of the semiconductor substrate through the NBL.

### Claim 19 (depends on 15)

The integrated circuit of claim 15, wherein the DT structures each include a dielectric sidewall and a polysilicon core.