# US 11,444,070 B2 · Semiconductor packages

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- Number: US 11,444,070 B2
- Document ID: US11444070B2
- Status: Granted
- Kind: B2
- Application number: 17/200,984
- Filed: 2021-03-15
- Published: 2021-11-04
- Granted: 2022-09-13
- Earliest claimed: 2020-05-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yongjin Park; Jiin Yu; Jin-San Jung
- Web page: https://patentgrep.com/patent/US11444070B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/0198: {batch processes}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07302: {using an auxiliary member}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07353: {changes in shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/354: {comprising polymers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and an adhesive layer between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a semiconductor substrate and a plurality of protection layers on the semiconductor substrate. The topmost layer of the protection layers may have a top surface with convex portions and concave portions, and the convex portions and the concave portions may be in contact with the adhesive layer.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor chip adhered to a second semiconductor chip by an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:
the first semiconductor chip comprises:
a semiconductor substrate; and
a first protection layer and a second protection layer sequentially stacked on the semiconductor substrate,
the first protection layer includes a plurality of holes defined therein, and
the second protection layer is in contact with the adhesive layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the second protection layer fills a portion of the holes defined in the first protection layer.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein each of the plurality of holes has a depth in a vertical direction orthogonal to an upper surface of the first protection layer, and a diameter in a horizontal direction parallel the upper surface of the first protection layer, where the depth is ½ to 1 times the diameter.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein:
the first protection layer has a mesh shaped configuration,
the first protection layer comprises a frame defined by the holes, and
a width of the frame is ½ to 1 times a diameter of the holes, when measured in a first direction.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein:
the first semiconductor chip further comprises a third protection layer, and
the third protection layer is interposed between the semiconductor substrate and the first protection layer.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the third protection layer comprises a material that is different from that of the first protection layer and is the same as that of the second protection layer.

### Claim 7 (depends on 5)

The semiconductor package of claim 5, wherein a thickness of the third protection layer is greater than a thickness of the first protection layer or a thickness of the second protection layer.

### Claim 8 (depends on 5)

The semiconductor package of claim 5, wherein a part of a top surface of the third protection layer is exposed by the holes, and a bottom surface of the second protection layer contacts part of the top surface of the exposed third protection layer.

### Claim 9 (depends on 5)

The semiconductor package of claim 5, wherein the first semiconductor chip further comprises a through-via penetrating the semiconductor substrate, the through-via extending vertically into the third protection layer and horizontally spaced apart from the second protection layer.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the level of the top surface of the first protection layer is substantially the same as the level of the top surface of the through-via.

### Claim 11

A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip on the first semiconductor chip; and
an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:
the first semiconductor chip comprises:
a semiconductor substrate; and
a plurality of protection layers on the semiconductor substrate,
a topmost layer among the protection layers has a top surface with convex portions and concave portions, and
the convex portions and the concave portions are in contact with the adhesive layer.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein:
the protection layers comprise a first protection layer and a second protection layer which are sequentially stacked on the semiconductor substrate,
the first protection layer comprises a frame defined by a plurality of holes,
the concave portions are vertically overlapped with the holes, and
the convex portions are vertically overlapped with the frame.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the frame has a width of 1 μm to 2 μm, each of the holes has a diameter of 1 μm to 2 μm, and each of the holes has a depth of 0.25 μm to 2 μm.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein:
the protection layers further comprise a third protection layer between the semiconductor substrate and the first protection layer, and
the first semiconductor chip further comprises a through-via penetrating the semiconductor substrate and the third protection layer.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the first semiconductor chip further comprises an upper pad connected to the through-via, and the upper pad vertically overlaps the third protection layer and does not overlap the first protection layer.

### Claim 16 (depends on 14)

The semiconductor package of claim 14, wherein a surface area of a top surface of the second protection layer is greater than a surface area of an upper surface of the third protection layer.

### Claim 17

A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip stacked on the first semiconductor chip; and
an adhesive layer between the first semiconductor chip and the second semiconductor, wherein:
the first semiconductor chip comprises:
a semiconductor substrate;
a through-via penetrating the semiconductor substrate;
a first protection layer and a second protection layer, which are sequentially stacked on the semiconductor substrate; and
an upper pad disposed on the second protection layer and connected to the through-via,
the first protection layer is provided to define a plurality of holes, and
a level of a bottom surface of the second protection layer is lower than a level of a top surface of the first protection layer, in a region overlapped with the holes.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein a level of a top surface of the second protection layer is lower than a level of an upper surface of the first protection layer in a region overlapping the holes.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein the adhesive layer comprises a non-conductive film.

### Claim 20 (depends on 17)

The semiconductor package of claim 17, wherein the first semiconductor chip comprises a logic chip and the second semiconductor chip comprises a memory chip.