# US 11,444,069 B2 · 3D semiconductor package including memory array

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- Number: US 11,444,069 B2
- Document ID: US11444069B2
- Status: Granted
- Kind: B2
- Application number: 17/138,270
- Filed: 2020-12-30
- Published: 2021-12-30
- Granted: 2022-09-13
- Earliest claimed: 2020-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bo-Feng Young; Sai-Hooi Yeong; Han-Jong Chia; Sheng-Chen Wang; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US11444069B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10W 90/00: Package configurations
- H10B 43/40: characterised by the peripheral circuit region
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/30: characterised by the memory core region
- H10B 51/40: characterised by the peripheral circuit region
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/80: characterised by the materials
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

## Claims

### Claim 1

A semiconductor device comprising:
a memory array comprising:
a gate dielectric layer contacting a first word line and a second word line; and
an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the gate dielectric layer is disposed between the OS layer and each of the first word line and the second word line;
an interconnect structure over the memory array, wherein a distance between the second word line and the interconnect structure is less than a distance between the first word line and the interconnect structure; and
an integrated circuit die bonded to the interconnect structure opposite the memory array, wherein the integrated circuit die is bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a length of the first word line is greater than a length of the second word line.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a front-side interconnect structure of the integrated circuit die is bonded to the interconnect structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a backside of the integrated circuit die is bonded to the interconnect structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the integrated circuit die comprises a through substrate via extending through a semiconductor substrate, the through substrate via electrically coupling a source/drain region of the integrated circuit die to the interconnect structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the interconnect structure comprises a first contact electrically coupling the first word line to the integrated circuit die, the first contact extending from the first word line to the integrated circuit die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a second integrated circuit die hybrid bonded to the interconnect structure adjacent the integrated circuit die.

### Claim 8

A device comprising:
a logic die comprising a semiconductor substrate;
an interconnect structure over the logic die; and
a memory array over the interconnect structure, the memory array comprising:
a first memory cell comprising a first portion of a gate dielectric layer contacting a first word line; and
a second memory cell comprising a second portion of the gate dielectric layer contacting a second word line, wherein the second memory cell is disposed further from the interconnect structure than the first memory cell in a first direction perpendicular to a major surface of the semiconductor substrate, wherein the second word line has a length in a second direction perpendicular to the first direction greater than a length of the first word line in the second direction, and wherein the logic die comprises circuits configured to perform read and write operations in the memory array.

### Claim 9 (depends on 8)

The device of claim 8, wherein the logic die is bonded to the interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

### Claim 10 (depends on 8)

The device of claim 8, wherein the logic die comprises a front-side interconnect structure, and wherein the front-side interconnect structure is bonded to the interconnect structure.

### Claim 11 (depends on 8)

The device of claim 8, wherein a backside of the logic die is bonded to the interconnect structure.

### Claim 12 (depends on 11)

The device of claim 11, wherein the logic die comprises a through substrate via electrically coupled to a source/drain region, wherein the through substrate via extends through a semiconductor substrate of the logic die, and wherein the semiconductor substrate and the through substrate via are bonded to the interconnect structure.

### Claim 13 (depends on 12)

The device of claim 12, wherein the interconnect structure comprises a contact extending from the through substrate via to the first word line.

### Claim 14

A method comprising:
forming a memory array, forming the memory array comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating conductive layers and dielectric layers;
patterning a first trench extending through the multi-layer stack;
depositing a gate dielectric layer along sidewalls and a bottom surface of the first trench, wherein the gate dielectric layer is deposited in contact with a first sidewall of a first conductive layer of the conductive layers;
depositing an oxide semiconductor (OS) layer over the gate dielectric layer;
forming a first interconnect structure over the memory array; and
bonding an integrated circuit device to the first interconnect structure using dielectric-to-dielectric bonding and metal-to-metal bonding.

### Claim 15 (depends on 14)

The method of claim 14, further comprising performing a read/write operation in the memory array, wherein the integrated circuit device controls the read/write operation.

### Claim 16 (depends on 14)

The method of claim 14, wherein a backside of the integrated circuit device is bonded to the first interconnect structure.

### Claim 17 (depends on 14)

The method of claim 14, wherein a plurality of integrated circuit devices on a wafer are bonded to the first interconnect structure, the plurality of integrated circuit devices comprising the integrated circuit device, wherein the method further comprises dicing the memory array and the wafer.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the memory array further comprises etching the conductive layers and the dielectric layers to form a staircase structure, wherein the conductive layers and the dielectric layers have decreasing lengths in a direction away from the substrate.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first interconnect structure is formed over the memory array opposite the substrate.

### Claim 20 (depends on 14)

The method of claim 14, wherein bonding the integrated circuit device to the first interconnect structure comprises bonding a front-side interconnect structure of the integrated circuit device to the first interconnect structure.