# US 11,444,067 B2 · Stacked interposer structures, microelectronic device assemblies including same, and methods of fabrication, and related electronic systems

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- Number: US 11,444,067 B2
- Document ID: US11444067B2
- Status: Granted
- Kind: B2
- Application number: 16/715,242
- Filed: 2019-12-16
- Published: 2021-06-17
- Granted: 2022-09-13
- Earliest claimed: 2019-12-16
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Owen R. Fay; Chan H. Yoo
- Web page: https://patentgrep.com/patent/US11444067B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/90: Bond pads, in general
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 90/295: {optical coupling}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

## Claims

### Claim 1

A stacked interposer structure, consisting of:
a first interposer comprising:
a first core comprising a semiconductor material;
a first redistribution structure comprising multiple redistribution layers (RDLs) over a side of the first core, the first redistribution structure configured for operably coupling, on a surface of the first redistribution structure, to one or more memory device stack locations and to a processor device location;
cache memory at least partially within the core adjacent the first redistribution structure under and operably coupled through the first redistribution structure to the processor device location; and
a first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core; and
a second interposer comprising:
a second core comprising a semiconductor material;
a second redistribution structure comprising multiple redistribution layers (RDLs) over a side of the second core and facing in a direction opposite a direction of the first redistribution structure;
a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core; and
the first and second redistribution structures being operably coupled through both the first set of TSVs and the second set of TSVs.

### Claim 2 (depends on 1)

The stacked interposer structure of claim 1, wherein the first redistribution structure and the second redistribution structure are cooperatively configured to, in combination, mutually operably couple the one or more memory device stack locations and the processor location and operably couple the one or more memory device stack locations to higher-level packaging through the second interposer.

### Claim 3 (depends on 1)

The stacked interposer structure of claim 1, wherein the second interposer is configured, on a surface thereof facing away from the first interposer, with conductive elements for operably coupling the stacked interposer structure to higher-level packaging.

### Claim 4 (depends on 1)

The stacked interposer structure of claim 1, wherein TSVs of the first interposer and TSVs of the second interposer are mutually aligned and operably coupled with discrete conductive elements.

### Claim 5 (depends on 1)

The stacked interposer structure of claim 1, wherein at least one of the first interposer and the second interposer comprises passive circuitry comprising at least one of capacitors, resistors or inductors over a core thereof, within the core thereof, or both.

### Claim 6 (depends on 1)

The stacked interposer structure of claim 1, wherein at least one of the first interposer and the second interposer comprises active circuitry comprising at least one of memory other than cache memory, logic, fuses, antifuses or a field programmable gate array.

### Claim 7 (depends on 1)

The stacked interposer structure of claim 1, wherein the first redistribution structure and the second redistribution structure comprise a same number of RDLs.

### Claim 8

A microelectronic device assembly, comprising:
a stacked interposer structure consisting of two directly interconnected, superimposed interposers, each interposer having a semiconductor core and a redistribution structure on one side thereof;
at least one host device and at least one memory device mounted on, and operably coupled to, a redistribution structure of one of the two interconnected interposers, the at least one host device operably coupled to cache memory at least partially within the semiconductor core of the one interposer under a location of the at least one host device through the redistribution structure of the one interposer; and
circuitry of the stacked interposer structure operably coupling the at least one host device and the at least one memory device and extending to a side of the stacked interposer structure opposite the at least one host device and the at least one memory device for connection to higher level packaging.

### Claim 9 (depends on 8)

The microelectronic device assembly of claim 8, wherein the at least one host device comprises a graphics processor unit (GPU), a central processing unit (CPU), a controller, or a system on a chip (SoC), and the at least one memory device comprises at least one of DRAM, SRAM, ferroelectric RAM (FeRAM), Resistive RAM (RRAM or ReRAM), phase change memory (PCM), 3D XPoint™ memory, NAND flash memory, or NOR flash memory.

### Claim 10 (depends on 8)

The microelectronic device assembly of claim 8, wherein the at least one host device comprises a graphics processor unit (GPU) and the at least one memory device comprises a high bandwidth memory device configured as a stack of high bandwidth DRAM die.

### Claim 11 (depends on 10)

The microelectronic device assembly of claim 10, wherein a core of one of the multiple interconnected interposers of the stacked interposer structure comprises logic circuitry for interfacing with the high bandwidth memory device.

### Claim 12 (depends on 8)

The microelectronic device assembly of claim 8, wherein the two interconnected interposers are interconnected by TSVs extending through the semiconductor core of at least one of the two interconnected interposers.

### Claim 13 (depends on 8)

The microelectronic device assembly of claim 8, wherein at least one of the multiple interconnected interposers comprises at least one of passive circuitry and active circuitry other than cache memory on a semiconductor core thereof.

### Claim 14 (depends on 13)

The microelectronic device assembly of claim 13, wherein the passive circuitry comprises at least one of capacitors, resistors or inductors, and the active circuitry comprises at least one of memory other than cache memory, logic, fuses, antifuses or a field programmable gate array.

### Claim 15 (depends on 8)

The microelectronic device assembly of claim 8, wherein the redistribution structure of each of the multiple interconnected interposers comprises multiple redistribution layers (RDLs).

### Claim 16 (depends on 15)

The microelectronic device assembly of claim 15, wherein each redistribution structure comprises a same number of redistribution layers (RDLs).

### Claim 17

An electronic system, comprising:
an input device and an output device, the electronic system further comprising:
a processor device and at least one memory device operably coupled to a redistribution structure of an interposer comprising a semiconductor core including cache memory circuitry located under the processor device and operably coupled thereto through the redistribution structure of the interposer, the redistribution structure of the interposer operably coupled to another redistribution structure of another interposer at least by through silicon vias (TSVs) extending from the redistribution structure of the interposer through the semiconductor core to a side thereof opposite the redistribution structure; and
the input device and the output device operably coupled to the processor through conductive paths of the another interposer.

### Claim 18 (depends on 17)

The electronic system of claim 17, wherein the at least one memory device comprises at least one stack of multiple high bandwidth memory die.